Datasheet 265
Functional Description
5.27.3 Support for Function Level Reset (FLR) in PCH
Intel VT-d allows system software (VMM/OS) to assign I/O devices to multiple domains.
The system software, then, requires ways to reset I/O devices or their functions within,
as it assigns/re-assigns I/O devices from one domain to another. The reset capability is
required to ensure the devices have undergone proper re-initialization and are not
keeping the stale state. A standard ability to reset I/O devices is also useful for the
VMM in case where a guest domain with assigned devices has become unresponsive or
has crashed.
PCI Express defines a form of device hot reset which can be initiated through the
Bridge Control register of the root/switch port to which the device is attached. How-
ever, the hot reset cannot be applied selectively to specific device functions. Also, no
similar standard functionality exists for resetting root-complex integrated devices.
Current reset limitations can be addressed through a function level reset (FLR) mecha-
nism that allows software to independently reset specific device functions.
5.27.4 Virtualization Support for PCH’s IOxAPIC
The Intel VT-d architecture extension requires Interrupt Messages to go through the
similar Address Remapping as any other memory requests. This is to allow domain
isolation for interrupts such that a device assigned in one domain is not allowed to
generate interrupts to another domain.
The Address Remapping for Intel VT-d is based on the Bus:Device:Function field
associated with the requests. Hence, it is required for the internal IOxAPIC to initiate
the Interrupt Messages using a unique Bus:Device:Function.
The PCH supports BIOS programmable unique Bus:Device:Function for the internal
IOxAPIC. The Bus:Device:Function field does not change the IOxAPIC functionality in
anyway, nor promoting IOxAPIC as a stand-alone PCI device. The field is only used by
the IOxAPIC in the following:
• As the Requestor ID when initiating Interrupt Messages to the processor
• As the Completer ID when responding to the reads targeting the IOxAPIC’s
Memory-Mapped I/O registers
5.27.5 Virtualization Support for High Precision Event Timer
(HPET)
The Intel VT-d architecture extension requires Interrupt Messages to go through the
similar Address Remapping as any other memory requests. This is to allow domain
isolation for interrupts such that a device assigned in one domain is not allowed to
generate interrupts to another domain.
The Address Remapping for Intel VT-d is based on the Bus:Device:Function field
associated with the requests. Hence, it is required for the HPET to initiate the direct
FSB Interrupt Messages using unique Bus:Device:Function.
The PCH supports BIOS programmable unique Bus:Device:Function for each of the
HPET timers. The Bus:Device:Function field does not change the HPET functionality in
anyway, nor promoting it as a stand-alone PCI device. The field is only used by the
HPET timer in the following:
• As the Requestor ID when initiating direct interrupt messages to the processor
• As the Completer ID when responding to the reads targeting its Memory-Mapped
registers
• The registers for the programmable Bus:Device:Function for HPET timer 7:0 reside
under the Device 31:Function 0 LPC Bridge’s configuration space.
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