Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - USB EHCI PCI Register Address Map (USB EHCI-D29:F0, D26:F0)

Datasheet 641
EHCI Controller Registers (D29:F0, D26:F0)
16 EHCI Controller Registers
(D29:F0, D26:F0)
16.1 USB EHCI Configuration Registers
(USB EHCI—D29:F0, D26:F0)
Note: Prior to BIOS initialization of the PCH USB subsystem, the EHCI controllers will appear
as Function 7. After BIOS initialization, the EHCI controllers will be Function 0.
Note: Register address locations that are not shown in Table 16-1 should be treated as
Reserved (see Section 9.2 for details).
Table 16-1. USB EHCI PCI Register Address Map (USB EHCI—D29:F0, D26:F0) (Sheet 1 of
2)
Offset Mnemonic Register Name Default Value Type
00h–01h VID Vendor Identification 8086h RO
02h–03h DID Device Identification
See register
description
RO
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 0290h R/WC, RO
08h RID Revision Identification
See register
description
RO
09h PI Programming Interface 20h RO
0Ah SCC Sub Class Code 03h RO
0Bh BCC Base Class Code 0Ch RO
0Dh PMLT Primary Master Latency Timer 00h RO
0Eh HEADTYP Header Type 80h RO
10h–13h MEM_BASE Memory Base Address 00000000h R/W, RO
2Ch–
2Dh
SVID
USB EHCI Subsystem Vendor
Identification
XXXXh R/W
2Eh–2Fh SID USB EHCI Subsystem Identification XXXXh R/W
34h CAP_PTR Capabilities Pointer 50h RO
3Ch INT_LN Interrupt Line 00h R/W
3Dh INT_PN Interrupt Pin
See register
description
RO
50h PWR_CAPID
PCI Power Management Capability
ID
01h RO
51h NXT_PTR1 Next Item Pointer 58h R/W
52h–53h PWR_CAP Power Management Capabilities C9C2h R/W
54h–55h PWR_CNTL_STS Power Management Control/Status 0000h
R/W, R/WC,
RO
58h DEBUG_CAPID Debug Port Capability ID 0Ah RO