Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - TCO I;O Register Address Map

LPC Interface Bridge Registers (D31:F0)
534 Datasheet
13.9 System Management TCO Registers
The TCO logic is accessed using registers mapped to the PCI configuration space
(Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers,
see LPC Device 31:Function 0 PCI Configuration registers.
TCO Register I/O Map
The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which
is, PMBASE + 60h in the PCI config space. The following table shows the mapping of
the registers within that 32-byte range. Each register is described in the following
sections.
13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register
I/O Address: TCOBASE +00h Attribute: R/W
Default Value: 0000h Size: 16-bit
Lockable: No Power Well: Core
Table 13-12. TCO I/O Register Address Map
TCOBASE
+ Offset
Mnemonic Register Name Default Type
00h–01h TCO_RLD
TCO Timer Reload and Current
Value
0000h R/W
02h TCO_DAT_IN TCO Data In 00h R/W
03h TCO_DAT_OUT TCO Data Out 00h R/W
04h–05h TCO1_STS TCO1 Status 0000h R/WC, RO
06h–07h TCO2_STS TCO2 Status 0000h R/WC
08h–09h TCO1_CNT TCO1 Control 0000h
R/W,
R/WLO, R/WC
0Ah–0Bh TCO2_CNT TCO2 Control 0008h R/W
0Ch–0Dh
TCO_MESSAGE1,
TCO_MESSAGE2
TCO Message 1 and 2 00h R/W
0Eh TCO_WDCNT Watchdog Control 00h R/W
0Fh — Reserved — —
10h SW_IRQ_GEN Software IRQ Generation 03h R/W
11h — Reserved — —
12h–13h TCO_TMR TCO Timer Initial Value 0004h R/W
14h–1Fh — Reserved — —
Bit Description
15:10 Reserved
9:0
TCO Timer Value — R/W. Reading this register will return the current count of the TCO
timer. Writing any value to this register will reload the timer to prevent the timeout.