Datasheet 535
LPC Interface Bridge Registers (D31:F0)
13.9.2 TCO_DAT_IN—TCO Data In Register
I/O Address: TCOBASE +02h Attribute: R/W
Default Value: 00h Size: 8-bit
Lockable: No Power Well: Core
13.9.3 TCO_DAT_OUT—TCO Data Out Register
I/O Address: TCOBASE +03h Attribute: R/W
Default Value: 00h Size: 8-bit
Lockable: No Power Well: Core
13.9.4 TCO1_STS—TCO1 Status Register
I/O Address: TCOBASE +04h Attribute: R/WC, RO
Default Value: 2000h ‘Size: 16-bit
Lockable: No Power Well: Core
(Except bit 7, in RTC)
Bit Description
7:0
TCO Data In Value — R/W. This data register field is used for passing commands from
the OS to the SMI handler. Writes to this register will cause an SMI and set the
SW_TCO_SMI bit in the TCO1_STS register (D31:F0:04h).
Bit Description
7:0
TCO Data Out Value — R/W. This data register field is used for passing commands
from the SMI handler to the OS. Writes to this register will set the TCO_INT_STS bit in
the TCO1_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL
bits.
Bit Description
15:14 Reserved
13
TCO_SLVSEL (TCO Slave Select) — RO. This register bit is Read Only by Host and
indicates the value of TCO Slave Select Soft Strap. Refer to the PCH Soft Straps section
of the SPI Chapter for details.
12
DMISERR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = PCH received a DMI special cycle message using DMI indicating that it wants to
cause an SERR#. The software must read the processor to determine the reason
for the SERR#.
11 Reserved
10
DMISMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = PCH received a DMI special cycle message using DMI indicating that it wants to
cause an SMI. The software must read the processor to determine the reason for
the SMI.
9
DMISCI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = PCH received a DMI special cycle message using DMI indicating that it wants to
cause an SCI. The software must read the processor to determine the reason for
the SCI.
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