Datasheet 891
Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.4 MEI1_MBAR—MEI0 MMIO Registers
These MMIO registers are accessible starting at the MEI1 MMIO Base Address
(MEI1_MBAR) which gets programmed into D22:F1:Offset 10–17h. These registers are
reset by PLTRST# unless otherwise noted.
23.4.1 H_CB_WW—Host Circular Buffer Write Window
(MEI MMIO Register)
Address Offset: MEI1_MBAR + 00h Attribute: RO
Default Value: 00000000h Size: 32 bits
Table 23-3. MEI MMIO Register Address Map (VE — D23:F0)
MEI_MBAR+
Offset
Mnemonic Register Name Default Type
00–03h H_CB_WW Host Circular Buffer Write Window 00000000h RO
04h–07h H_CSR Host Control Status 02000000h
R/W, R/WC,
RO
08h–0Bh ME_CB_RW ME Circular Buffer Read Window 00000000h RO
0Ch–0Fh ME CSR_HA ME Control Status Host Access 02000000h RO
Bit Description
31:0
Host Circular Buffer Write Window Field (H_CB_WWF). This bit field is for host to
write into its circular buffer. The host's circular buffer is located at the ME subsystem
address specified in the Host CB Base Address register. This field is write only, reads will
return arbitrary data. Writes to this register will increment the H_CBWP as long as
ME_RDY is 1. When ME_RDY is 0, writes to this register have no effect and are not
delivered to the H_CB, nor is H_CBWP incremented.
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