Datasheet 231
Functional Description
5.21.2.2 I
2
C Write Commands to the Intel
®
ME
Table 5-53 lists the write commands supported by the Intel ME.
All bits in the write commands must be written to the PCH or the operation will be
aborted. For example, for 6-bytes write commands, all 48 bits must be written or the
operation will be aborted.
The command format follows the Block Write format of the SMBus specification.
5.21.2.3 Block Read Command
The external controller may read thermal information from the PCH using the SMBus
Block Read Command. Byte-read and Word-read SMBus commands are not supported.
Note that the reads use a different address than the writes.
The command format follows the Block Read format of the SMBus specification.
The PCH and external controller are set up by BIOS with the length of the read that is
supported by the platform. The device must always do reads of the lengths set up by
BIOS.
The PCH supports any one of the following lengths: 2, 4, 5, 9, 10, 14 or 20 bytes. The
data always comes in the order described in Table 5-53, where 0 is the first byte
received in time on the SMBus.
Table 5-53. I
2
C Write Commands to the Intel ME
Transaction
Slave
Addr
Data Byte0
(Command)
Data
Byte 1
(Byte
Count)
Data
Byte 2
Data
Byte 3
Data
Byte 4
Data
Byte 5
Data
Byte 6
Data
Byte 7
Write
Processor
Temp Limits
I
2
C42h4h
Lower
Limit
[15:8]
Lower
Limit
[7:0]
Upper
Limit
[15:8]
Upper
Limit
[7:0]
Write PCH
Temp Limits
I
2
C44h2h
Lower
Limit
[7:0]
Upper
Limit
[7:0]
Write DIMM
Temp Limits
I
2
C45h2h
Lower
Limit
[7:0]
Upper
Limit
[7:0]