Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

Datasheet 87
Signal Description
2.27 Pin Straps
The following signals are used for static configuration. They are sampled at the rising
edge of PWROK to select configurations (except as noted), and then revert later to their
normal usage. To invoke the associated mode, the signal should be driven at least four
PCI clocks prior to the time it is sampled.
The PCH implements Soft Straps, which are used to configure specific functions within
the PCH and processor very early in the boot process before BIOS or SW intervention.
When Descriptor Mode is enabled, the PCH will read Soft Strap data out of the SPI
device prior to the deassertion of reset to both the Intel Management Engine and the
Host system. Please refer to Section 5.24.2 for information on Descriptor Mode
Table 2-27. Functional Strap Definitions (Sheet 1 of 5)
Signal Usage
When
Sampled
Comment
SPKR No Reboot
Rising edge of
PWROK
The signal has a weak internal pull-down. Note:
the internal pull-down is disabled after PLTRST#
deasserts. If the signal is sampled high, this
indicates that the system is strapped to the “No
Reboot” mode (PCH will disable the TCO Timer
system reboot feature). The status of this strap
is readable using the NO REBOOT bit (Chipset
Config Registers: Offset 3410h:Bit 5).
INIT3_3V# Reserved
Rising edge of
PWROK
This signal has a weak internal pull-up. Note: the
internal pull-up is disabled after PLTRST#
deasserts.
NOTE: This signal should not be pulled low
GNT3# /GPIO55
Top-Block Swap
Override
Rising edge of
PWROK
The signal has a weak internal pull-up. Note: the
internal pull-up is disabled after PLTRST#
deasserts. If the signal is sampled low, this
indicates that the system is strapped to the
“topblock swap” mode (PCH inverts A16 for all
cycles targeting BIOS space).
The status of this strap is readable using the Top
Swap bit (Chipset Config Registers: Offset
3414h:Bit 0). Note that software will not be able
to clear the Top-Swap bit until the system is
rebooted without GNT3# being pulled down.
INTVRMEN
Integrated 1.05
V VRM Enable /
Disable
Always
Integrated 1.05 V VRMs is enabled when high
External VR power source is used for DcpSus
when sampled low.
NOTE: External VR powering option is for Mobile
Only. Other systems should not pull the
strap low.

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General

Brand	Intel
Model	6 SERIES CHIPSET - DATASHEET 01-2011
Category	Controller
Language	English