Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

Functional Description
144 Datasheet
Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2,
IRQ8#, and IRQ13.
Note: Active-low interrupt sources (such as, the PIRQ#s) are inverted inside the PCH. In the
following descriptions of the 8259s, the interrupt levels are in reference to the signals
at the internal interface of the 8259s, after the required inversions have occurred.
Therefore, the term “high” indicates “active,” which means “low” on an originating
PIRQ#.
5.8.1 Interrupt Handling
5.8.1.1 Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each
interrupt level. These bits are used to determine the interrupt vector returned, and
status of any other pending interrupts. Table 5-16 defines the IRR, ISR, and IMR.
5.8.1.2 Acknowledging Interrupts
The processor generates an interrupt acknowledge cycle that is translated by the host
bridge into a PCI Interrupt Acknowledge Cycle to the PCH. The PIC translates this
command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the
first internal INTA# pulse to freeze the state of the interrupts for priority resolution. On
the second INTA# pulse, the master or slave sends the interrupt vector to the
processor with the acknowledged interrupt code. This code is based upon Bits [7:3] of
the corresponding ICW2 register, combined with three bits representing the interrupt
within that controller.
Table 5-16. Interrupt Status Registers
Bit Description
IRR
Interrupt Request Register. This bit is set on a low to high transition of the interrupt
line in edge mode, and by an active high level in level mode. This bit is set whether or
not the interrupt is masked. However, a masked interrupt will not generate INTR.
ISR
Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared,
when an interrupt acknowledge cycle is seen, and the vector returned is for that
interrupt.
IMR
Interrupt Mask Register. This bit determines whether an interrupt is masked.
Masked interrupts will not generate INTR.
Table 5-17. Content of Interrupt Vector Byte
Master, Slave Interrupt Bits [7:3] Bits [2:0]
IRQ7,15
ICW2[7:3]
111
IRQ6,14 110
IRQ5,13 101
IRQ4,12 100
IRQ3,11 011
IRQ2,10 010
IRQ1,9 001
IRQ0,8 000

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General

Brand	Intel
Model	6 SERIES CHIPSET - DATASHEET 01-2011
Category	Controller
Language	English