Datasheet 205
Functional Description
5.18.3 USB 2.0 Enhanced Host Controller DMA
The PCH USB 2.0 EHC implements three sources of USB packets. They are, in order of
priority on USB during each microframe:
1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port),
2. The Periodic DMA engine, and
3. The Asynchronous DMA engine.
The PCH always performs any currently-pending debug port transaction at the
beginning of a microframe, followed by any pending periodic traffic for the current
microframe. If there is time left in the microframe, then the EHC performs any pending
asynchronous traffic until the end of the microframe (EOF1). Note that the debug port
traffic is only presented on Port 1 and Port 9, while the other ports are idle during this
time.
5.18.4 Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
5.18.5 Packet Formats
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
The PCH EHCI allows entrance to USB test modes, as defined in the USB 2.0
specification, including Test J, Test Packet, etc. However note that the PCH Test Packet
test mode interpacket gap timing may not meet the USB 2.0 specification.
5.18.6 USB 2.0 Interrupts and Error Conditions
Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial
Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that
cause them. All error conditions that the EHC detects can be reported through the EHCI
Interrupt status bits. Only PCH-specific interrupt and error-reporting behavior is
documented in this section. The EHCI Interrupts Section must be read first, followed by
this section of the datasheet to fully comprehend the EHC interrupt and error-reporting
functionality.
• Based on the EHC Buffer sizes and buffer management policies, the Data Buffer
Error can never occur on the PCH.
• Master Abort and Target Abort responses from hub interface on EHC-initiated read
packets will be treated as Fatal Host Errors. The EHC halts when these conditions
are encountered.
• The PCH may assert the interrupts which are based on the interrupt threshold as
soon as the status for the last complete transaction in the interrupt interval has
been posted in the internal write buffers. The requirement in the Enhanced Host
Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the
status is written to memory) is met internally, even though the write may not be
seen on DMI before the interrupt is asserted.
• Since the PCH supports the 1024-element Frame List size, the Frame List Rollover
interrupt occurs every 1024 milliseconds.
• The PCH delivers interrupts using PIRQH#.
• The PCH does not modify the CERR count on an Interrupt IN when the “Do
Complete-Split” execution criteria are not met.
• For complete-split transactions in the Periodic list, the “Missed Microframe” bit does
not get set on a control-structure-fetch that fails the late-start test. If subsequent
accesses to that control structure do not fail the late-start test, then the “Missed
Microframe” bit will get set and written back.
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