Figure 8-3. S5 to S0 Timing Diagram
APWROK may come up earlier
than PWROK, but no later
SLP_S3#
SLP_A#
Signal NameDestSource
SLP_S4#
SLP_S5#
PCH Board
PCH Board
PCH Board
PCH Board
Board PCH
VccCore_CPUBoard CPU
PROCPWRGD
SUS_STAT#
PWROK
DRAMPWROK
SYS_PWROKCPU VRM PCH
Board PCH
PCH CPU
APWROKBoard PCH
VccBoard PCH
25 MHz
Crystal Osc
Board PCH
stable
t209
PLTRST#
DMI
PCH CPU
PCH Board
PCH CPU/Board
PCH CPU
t203
t204
t205
t207
T
r
a
i
n
i
n
g
S
T
R
A
P
_
S
E
T
C
P
U
_
R
E
S
E
T
_
D
O
N
E
F
l
e
x
S
K
U
V
D
M
w
r
it
e
s
C
P
U
_
R
E
S
E
T
_
D
O
N
E
_
A
C
K
t211
t206
V_vid
t210
SLP_LAN#PCH Board
Could already be high before this sequence begins (to support WOL),
but will never go high later than SLP_S3# or SLP_A#
VccASW
Could already be high before this sequence begins (to support M3),
but will never go high later than SLP_S3#
THRMTRIP#CPU PCH
ignored honored
Assumes soft strap programmed to start at
PROCPWRGD - expected setting for SNB
CPU SVIDCPU CPU VRM
Serial VID
Load
PROCPWRGD
t208
stable
PCH
Output Clocks
PCH Board
t229
t230
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