Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Thermal Memory Mapped Configuration Register Address Map

Thermal Sensor Registers (D31:F6)
854 Datasheet
22.2 Thermal Memory Mapped Configuration Registers
(Thermal Sensor – D31:F26)
The base memory for these thermal memory mapped configuration registers is
specified in the TBARB (D31:F6:Offset 40h). The individual registers are then
accessible at TBARB + Offset.
Table 22-2. Thermal Memory Mapped Configuration Register Address Map
Offset Mnemonic Register Name Default Type
0h TSIU Thermal Sensor In Use 00h RO,R/W
1h TSE Thermal Sensor Enable 00h R/W
2h TSS Thermal Sensor Status 00h R/W
3h TSTR Thermal Sensor Thermometer Read FFh RO
4h TSTTP Thermal Sensor Temperature Trip Point 00000000h R/W
8h TSC0 Thermal Sensor Catastrophic Lock Down 00h R/W
0Ch TSES Thermal Sensor Error Status 00h R/WC
0Dh TSGPEN
Thermal Sensor General Purpose Event
Enable
00h R/W
0Eh TSPC Thermal Sensor Policy Control 00h R/W, RO
14h PTA PCH Temperature Adjust 0000h R/W
1Ah TRC Thermal Reporting Control 0000h R/W
3Fh AE Alert Enable 00h R/W
56h PTL Processor Temperature Limit 0000h R/W
60h PTV Processor Temperature Value 0000h RO
70h PHL PCH Hot Level 00h R/W
82h TSPIEN
Thermal Sensor PCI Interrupt Event
enable
00h R/W
83h TSLOCK Thermal Sensor Register Lock Control 00h R/W
ACh TC2 Thermal Compares 2 00000000h RO
B0 DTV DIMM Temperature Values 00000000h RO
D8h ITV Internal Temperature Values 00000000h RO