Datasheet 117
Functional Description
5 Functional Description
This chapter describes the functions and interfaces of the PCH.
5.1 DMI-to-PCI Bridge (D30:F0)
The DMI-to-PCI bridge resides in PCI Device 30, Function 0 on Bus 0. This portion of
the PCH implements the buffering and control logic between PCI and Direct Media
Interface (DMI). The PCI decoder in this device must decode the ranges for the DMI. All
register contents are lost when core well power is removed.
Direct Media Interface (DMI) is the chip-to-chip connection between the processor and
the PCH. This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic and true isochronous transfer capabilities. Base
functionality is completely software transparent permitting current and legacy software
to operate normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS)
transactions, the PCH supports two virtual channels on DMI—VC0 and VC1. These two
channels provide a fixed arbitration scheme where VC1 is always the highest priority.
VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be
specifically enabled and configured at both ends of the DMI link (that is, the PCH and
processor).
Configuration registers for DMI, virtual channel support, and DMI active state power
management (ASPM) are in the RCRB space in the Chipset Config Registers
(Chapter 10).
5.1.1 PCI Legacy Mode
Native PCI functionality is not supported requiring methods such as using PCIe-to-PCI
bridges to enable external PCI I/O devices. To be able to use PCIe-to-PCI bridges and
attached legacy PCI devices, the PCH provides PCI Legacy Mode. PCI Legacy Mode
allows both the PCI Express root port and PCIe-to-PCI bridge look like subtractive PCI-
to-PCI bridges. This allows the PCI Express root port to subtractively decode and
forward legacy cycles to the bridge, and the PCIe-to-PCI bridge continues forwarding
legacy cycles to downstream PCI devices. For designs that would like to utilize PCI
Legacy Mode, BIOS must program registers in the DMI-to-PCI bridge (Device
30:Function 0) and in the desired PCI Express Root Port (Device 28:Functions 0-7) to
enable subtractive decode.
Note: Software must ensure that only one PCH device is enabled for Subtractive decode at a
time.
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