Datasheet 239
Functional Description
5. The HD Audio controller then asserts the HDA_DOCK_EN# signal so that the Bit
Clock signal begins toggling to the dock codec. HDA_DOCK_EN# shall be asserted
synchronously to Bit Clock and timed such that Bit Clock is low, SYNC is low, and
SDO is low. Pull-down resistors on these signals in the docking station discharge
the signals low so that when the state of the signal on both sides of the switch is
the same when the switch is turned on. This reduces the potential for charge
coupling glitches on these signals. Note that in the PCH the first 8 bits of the
Command field are “reserved” and always driven to 0's. This creates a predictable
point in time to always assert HDA_DOCK_EN#. Note that the HD Audio link reset
exit specification that requires that SYNC and SDO be driven low during Bit Clock
startup is not ensured. Note also that the SDO and Bit Clock signals may not be low
while HDA_DOCK_RST# is asserted which also violates the specification.
6. After the controller asserts HDA_DOCK_EN# it waits for a minimum of 2400 Bit
Clocks (100 µs) and then deasserts HDA_DOCK_RST#. This is done in such a way
to meet the HD Audio link reset exit specification. HDA_DOCK_RST# deassertion
should be synchronous to Bit Clock and timed such that there are least 4 full Bit
ClockS from the deassertion of HDA_DOCK_RST# to the first frame SYNC
assertion.
7. The Connect/Turnaround/Address Frame hardware initialization sequence will now
occur on the dock codecs' SDI signals. A dock codec is detected when SDI is high
on the last Bit Clock cycle of the Frame Sync of a Connect Frame. The appropriate
bit(s) in the State Change Status (STATESTS) register will be set. The Turnaround
and Address Frame initialization sequence then occurs on the dock codecs' SDI(s).
8. After this hardware initialization sequence is complete (approximately 32 frames),
the controller hardware sets the DCKSTS.DM bit to 1 indicating that the dock is now
mated. ACPI BIOS polls the DCKSTS.DM bit and when it detects it is set to 1,
conveys this to the OS through a plug-N-play IRP. This eventually invokes the HD
Audio Bus Driver, which then begins it's codec discovery, enumeration, and
configuration process.
9. Alternatively to step #8, the HD Audio Bus Driver may choose to enable an
interrupt by setting the WAKEEN bits for SDINs that didn't originally have codecs
attached to them. When a corresponding STATESTS bit gets set an interrupt will be
generated. In this case the HD Audio Bus Driver is called directly by this interrupt
instead of being notified by the plug-N-play IRP.
10.Intel HD Audio Bus Driver software “discovers” the dock codecs by comparing the
bits now set in the STATESTS register with the bits that were set prior to the
docking event.
5.22.1.2 Exiting D3/CRST# When Docked
1. In D3/CRST#, CRST# is asserted by the HD Audio Bus Driver. CRST# asserted
resets the dock state machines, but does not reset the DCKCTL.DA bit. Because the
dock state machines are reset, the dock is electrically isolated (HDA_DOCK_EN#
deasserted) and DOCK_RST# is asserted.
2. The Bus Driver clears the STATESTS bits, then deasserts CRST#, waits
approximately 7 ms, then checks the STATESTS bits to see which codecs are
present.
3. When CRST# is deasserted, the dock state machine detects that DCKCTL.DA is still
set and the controller hardware sequences through steps to electrically connect the
dock by asserting HDA_DOCK_EN# and then eventually deasserts DOCK_RST#.
This completes within the 7ms mentioned in step 2).
4. The Bus Driver enumerates the codecs present as indicated using the STATESTS
bits.
5. Note that this process did not require BIOS or ACPI BIOS to set the DCKCTL.DA bit.
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