Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - High Definition Audio Link; High Definition Audio Link Signals; Intel

Signal Description
70 Datasheet
2.14 Intel
®
High Definition Audio Link
Table 2-14. Intel
®
High Definition Audio Link Signals
Name Type Description
HDA_RST# O
Intel
®
High Definition Audio Reset: Master hardware reset to
external codec(s).
HDA_SYNC O
Intel
High Definition Audio Sync: 48 kHz fixed rate sample
sync to the codec(s). Also used to encode the stream number.
NOTE: This signal is sampled as a functional strap. See
Section 2.27 for more details. There is a weak integrated
pull-down resistor on this pin.
HDA_BCLK O
Intel High Definition Audio Bit Clock Output: 24.000 MHz
serial data clock generated by the Intel High Definition Audio
controller (the PCH).
HDA_SDO O
Intel High Definition Audio Serial Data Out: Serial TDM data
output to the codec(s). This serial output is double-pumped for a
bit rate of 48 Mb/s for Intel High Definition Audio.
NOTE: This signal is sampled as a functional strap. See
Section 2.27 for more details. There is a weak integrated
pull-down resistor on this pin.
HDA_SDIN[3:0] I
Intel High Definition Audio Serial Data In [3:0]: Serial TDM
data inputs from the codecs. The serial input is single-pumped
for a bit rate of 24 Mb/s for Intel High Definition Audio. These
signals have integrated pull-down resistors, which are always
enabled.
NOTE: During enumeration, the PCH will drive this signal. During
normal operation, the CODEC will drive it.
HDA_DOCK_EN#
/GPIO33
O
Intel High Definition Audio Dock Enable: This signal controls
the external Intel HD Audio docking isolation logic. This is an
active low signal. When deasserted the external docking switch is
in isolate mode. When asserted the external docking switch
electrically connects the Intel HD Audio dock signals to the
corresponding PCH signals.
This signal can instead be used as GPIO33.
HDA_DOCK_RST#
/ GPIO13
O
Intel High Definition Audio Dock Reset: This signal is a
dedicated HDA_RST# signal for the codec(s) in the docking
station. Aside from operating independently from the normal
HDA_RST# signal, it otherwise works similarly to the HDA_RST#
signal.
This signal is shared with GPIO13. This signal defaults to GPIO13
mode after PLTRST# and will be in the low state after PLTRST#.
BIOS is responsible for configuring GPIO13 to HDA_DOCK_RST#
mode.