Datasheet 447
LPC Interface Bridge Registers (D31:F0)
13 LPC Interface Bridge Registers
(D31:F0)
The LPC bridge function of the PCH resides in PCI Device 31:Function 0. This function
contains many other functional units, such as DMA and Interrupt controllers, Timers,
Power Management, System Management, GPIO, RTC, and LPC Configuration
Registers.
Registers and functions associated with other functional units are described in their
respective sections.
13.1 PCI Configuration Registers (LPC I/F—D31:F0)
Note: Address locations that are not shown should be treated as Reserved.
.
Table 13-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Type
00h–01h VID Vendor Identification 8086h RO
02h–03h DID Device Identification
See register
description
RO
04h–05h PCICMD PCI Command 0007h R/W, RO
06h–07h PCISTS PCI Status 0210h R/WC, RO
08h RID Revision Identification
See register
description
R/WO
09h PI Programming Interface 00h RO
0Ah SCC Sub Class Code 01h RO
0Bh BCC Base Class Code 06h RO
0Dh PLT Primary Latency Timer 00h RO
0Eh HEADTYP Header Type 80h RO
2Ch–2Fh SS Sub System Identifiers 00000000h R/WO
40h–43h PMBASE ACPI Base Address 00000001h R/W, RO
44h ACPI_CNTL ACPI Control 00h R/W
48h–4Bh GPIOBASE GPIO Base Address 00000001h R/W, RO
4C GC GPIO Control 00h R/W
60h–63h PIRQ[n]_ROUT PIRQ[A–D] Routing Control 80808080h R/W
64h SIRQ_CNTL Serial IRQ Control 10h R/W, RO
68h–6Bh PIRQ[n]_ROUT PIRQ[E–H] Routing Control 80808080h R/W
6Ch–6Dh LPC_IBDF IOxAPIC Bus:Device:Function 00F8h R/W
70h–7F HPET Configuration
80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W
82h–83h LPC_EN LPC I/F Enables 0000h R/W
84h–87h GEN1_DEC LPC I/F Generic Decode Range 1 00000000h R/W
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