EHCI Controller Registers (D29:F0, D26:F0)
678 Datasheet
16.2.3 USB 2.0-Based Debug Port Registers
The Debug port’s registers are located in the same memory area, defined by the Base
Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the
debug port registers (A0h) is declared in the Debug Port Base Offset Capability Register
at Configuration offset 5Ah (D29:F0, D26:F0:offset 5Ah). The specific EHCI port that
supports this debug capability (Port 1 for D29:F0 and Port 9 for D26:F0) is indicated by
a 4-bit field (bits 20–23) in the HCSPARAMS register of the EHCI controller. The address
map of the Debug Port registers is shown in Table 16-4.
NOTES:
1. All of these registers are implemented in the core well and reset by PLTRST#, EHC
HCRESET, and a EHC D3-to-D0 transition.
2. The hardware associated with this register provides no checks to ensure that software
programs the interface correctly. How the hardware behaves when programmed
improperly is undefined.
Table 16-4. Debug Port Register Address Map
MEM_BASE +
Offset
Mnemonic Register Name Default Type
A0–A3h CNTL_STS Control/Status 00000000h
R/W, R/WC,
RO
A4–A7h USBPID USB PIDs 00000000h R/W, RO
A8–AFh DATABUF[7:0] Data Buffer (Bytes 7:0)
00000000
00000000h
R/W
B0–B3h CONFIG Configuration 00007F01h R/W
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