Datasheet 171
Functional Description
5.13.7.6 Deep S4/S5
To minimize power consumption while in S4/S5, the PCH supports a lower power, lower
featured version of these power states known as Deep S4/S5. In these Deep S4 and
Deep S5 states, the Suspend wells are powered off, while the new Deep S4/S5 Well
(DSW) remains powered. A limited set of wake events are supported by the logic
located in the DSW.
The Deep S4/S5 capability and the SUSPWRDNACK pin functionality are mutually
exclusive.
5.13.7.6.1 Entry Into Deep S4/S5
A combination of conditions is required for entry into Deep S4/S5.
All of the following must be met:
— Intel ME in Moff
— AND either A or B as defined below:
a. ((DPS4_EN_AC AND S4) OR (DPS5_EN_AC AND S5)) (desktop only)
b. ((AC_PRESENT = 0) AND ((DPS4_EN_DC AND S4) OR (DPS5_EN_DC AND S5)))
Table 5-31. Transitions Due to Power Failure
State at Power Failure AFTERG3_EN bit Transition When Power Returns
S0, S1, S3
1
0
S5
S0
S4
1
0
S4
S0
Deep S4
1
0
Deep S4
S0
S5
1
0
S5
S0
Deep S5
1
0
Deep S5
S0
Table 5-32. Supported Deep S4/S5 Policy Configurations
Configuration DPS4_EN_DC DPS4_EN_AC DPS5_EN_DC DPS5_EN_AC
1: Enabled in S5 when on
Battery (ACPRESENT = 0)
0010
2: Enabled in S5 (ACPRESENT
not considered) (desktop only)
0011
3: Enabled in S4 and S5 when
on Battery (ACPRESENT = 0)
1010
4: Enabled in S4 and S5
(ACPRESENT not
considered) (desktop only
1111
5: Deep S4 / S5 disabled 0000
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