LPC Interface Bridge Registers (D31:F0)
516 Datasheet
13.8.3 Power Management I/O Registers
Table 13-11 shows the registers associated with ACPI and Legacy power management
support. These registers locations are all offsets from the ACPI base address defined in
the PCI Device 31: Function 0 space (PMBASE), and can be moved to any 128-byte
aligned I/O location. In order to access these registers, the ACPI Enable bit (ACPI_EN)
must be set. The registers are defined to support the ACPI 4.0a specification and
generally use the same bit names.
Note: All reserved bits and registers will always return 0 when read, and will have no effect
when written.
Table 13-11. ACPI and Legacy I/O Register Map
PMBASE
+ Offset
Mnemonic Register Name Default Type
00h–01h PM1_STS PM1 Status 0000h R/WC
02h–03h PM1_EN PM1 Enable 0000h R/W
04h–07h PM1_CNT PM1 Control 00000000h R/W, WO
08h–0Bh PM1_TMR PM1 Timer xx000000h RO
20h–27h GPE0_STS General Purpose Event 0 Status
0000000000
000000h
R/WC
28h–2Fh GPE0_EN
General Purpose Event 0
Enables
00000000
00000000h
R/W
30h–33h SMI_EN SMI# Control and Enable 00000002h
R/W, WO,
R/WO
34h–37h SMI_STS SMI Status 00000000h R/WC, RO
38h–39h ALT_GP_SMI_EN Alternate GPI SMI Enable 0000h R/W
3Ah–3Bh ALT_GP_SMI_STS Alternate GPI SMI Status 0000h R/WC
3Ch–3Dh UPRWC
USB Per-Port Registers Write
Control
0000h
R/WC, R/W,
R/WO
42h GPE_CNTL General Purpose Event Control 00h R/W
44h–45h DEVACT_STS Device Activity Status 0000h R/WC
50h PM2_CNT PM2 Control 00h R/W
60h–7Fh — Reserved for TCO — —
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