Functional Description
166 Datasheet
5.13.5 C-States
PCH-based systems implement C-states by having the processor control the states. The
chipset exchanges messages with the processor as part of the C-state flow, but the
chipset does not directly control any of the processor impacts of C-states, such as
voltage levels or processor clocking. In addition to the new messages, the PCH also
provides additional information to the processor using a sideband pin (PMSYNCH). All of
the legacy C-state related pins (STPCLK#, STP_CPU#, DPRSLP#, DPRSLPVR#, etc.) do
not exist on the PCH.
5.13.6 Dynamic PCI Clock Control (Mobile Only)
The PCI clock can be dynamically controlled independent of any other low-power state.
This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile
Design Guide, and is transparent to software.
The Dynamic PCI Clock control is handled using the following signals:
• CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run
• STP_PCI#: Used to stop the system PCI clock
Note: The 33-MHz clock to the PCH is “free-running” and is not affected by the STP_PCI#
signal.
Note: STP_PCI# is only used if PCI/LPC clocks are distributed from clock synthesizer rather
than PCH.
5.13.6.1 Conditions for Checking the PCI Clock
When there is a lack of PCI activity the PCH has the capability to stop the PCI clocks to
conserve power. “PCI activity” is defined as any activity that would require the PCI
clock to be running.
Any of the following conditions will indicate that it is not okay to stop the PCI clock:
• Cycles on PCI or LPC
• Cycles of any internal device that would need to go on the PCI bus
•SERIRQ activity
Behavioral Description
• When there is a lack of activity (as defined above) for 29 PCI clocks, the PCH
deasserts (drive high) CLKRUN# for 1 clock and then tri-states the signal.
5.13.6.2 Conditions for Maintaining the PCI Clock
PCI masters or LPC devices that wish to maintain the PCI clock running will observe the
CLKRUN# signal deasserted, and then must re-assert if (drive it low) within 3 clocks.
• When the PCH has tri-stated the CLKRUN# signal after deasserting it, the PCH then
checks to see if the signal has been re-asserted (externally).
• After observing the CLKRUN# signal asserted for 1 clock, the PCH again starts
asserting the signal.
• If an internal device needs the PCI bus, the PCH asserts the CLKRUN# signal.
5.13.6.3 Conditions for Stopping the PCI Clock
• If no device re-asserts CLKRUN# once it has been deasserted for at least 6 clocks,
the PCH stops the PCI clock by asserting the STP_PCI# signal to the clock
synthesizer.
• For case when PCH distribute PCI clock, PCH stop PCI clocks without the
involvement of STP_PCI#.
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