Datasheet 63
Signal Description
2.8 Power Management Interface
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
I
Overcurrent Indicators: These signals set corresponding bits in the
USB controllers to indicate that an overcurrent condition has occurred.
OC[7:0]# may optionally be used as GPIOs.
NOTES:
1. OC# pins are not 5 V tolerant.
2. Depending on platform configuration, sharing of OC# pins may
be required.
3. OC[3:0]# can only be used for EHCI Controller 1
4. OC[4:7]# can only be used for EHCI Controller 2
USBRBIAS O
USB Resistor Bias: Analog connection point for an external resistor.
Used to set transmit currents and internal load resistors.
USBRBIAS# I
USB Resistor Bias Complement: Analog connection point for an
external resistor. Used to set transmit currents and internal load
resistors.
Table 2-8. Power Management Interface Signals (Sheet 1 of 4)
Name Type Description
ACPRESENT
/ GPIO31
I
ACPRESENT: This input pin indicates when the platform is
plugged into AC power or not. In addition to the previous Intel
®
ME
to EC communication, the PCH uses this information to implement
the Deep S4/S5 policies. For example, the platform may be
configured to enter Deep S4/S5 when in S4 or S5 and only when
running on battery. This is powered by Deep S4/S5 Well.
This signal is muxed with GPIO31.
APWROK I
Active Sleep Well (ASW) Power OK: When asserted, indicates
that power to the ASW sub-system is stable.
BATLOW#
(Mobile Only) /
GPIO72
I
Battery Low: An input from the battery to indicate that there is
insufficient power to boot the system. Assertion will prevent wake
from S3–S5 state. This signal can also be enabled to cause an
SMI# when asserted.
NOTE: See Table 2.24 for Desktop implementation pin
requirements.
BMBUSY#
/ GPIO0
I
Bus Master Busy: Generic bus master activity indication driven
into the PCH. Can be configured to set the PM1_STS.BM_STS bit.
Can also be configured to assert indications transmitted from the
PCH to the processor using the PMSYNCH pin.
CLKRUN#
(Mobile Only) /
GPIO32 (Desktop
Only)
I/O
PCI Clock Run: Used to support PCI CLKRUN protocol. Connects
to peripherals that need to request clock restart or prevention of
clock stopping.
DPWROK I
DPWROK: Power OK Indication for the VccDSW3_3 voltage rail.
This input is tied together with RSMRST# on platforms that do not
support Deep S4/S5.
This signal is in the RTC well.
Table 2-7. USB Interface Signals (Sheet 2 of 2)
Name Type Description
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