Intel 6 SERIES CHIPSET - DATASHEET 01-2011

PCH Pin States
102 Datasheet
Power Management
CLKRUN#
19
Core Low Low Defined Defined Off Off
PLTRST# Suspend Low High High High Low Low
SLP_A#
5
Suspend Low High High High Defined Defined
SLP_S3# Suspend Low High High High Low Low
SLP_S4# Suspend Low High High High High Defined
SLP_S5#/GPIO63 Suspend Low High High High High Defined
2
SUS_STAT#/GPIO61 Suspend Low High High High Low Low
SUSCLK/GPIO62 Suspend Low Running
SUSWARN#/
SUSPWRDNACK/
GPIO30 (note 20)
Suspend 0 1 Defined Defined Defined Defined
SUSWARN#/
SUSPWRDNACK/
GPIO30 (note 21)
Suspend 0 1 1 1 1 1
DRAMPWROK Suspend Low High-Z High-Z High-Z High-Z Low
LAN_PHY_PWR_CTRL
9
/GPIO12
Suspend Low Low Defined Defined Defined Defined
PMSYNCH Core Low Low
Defined/
Low
10
Defined Off Off
STP_PCI#/GPIO34 Core
High-Z
(Input)
High-Z (Input) Defined Defined Off Off
SLP_LAN#
14
/GPIO29
SLP_LAN# (using
soft-strap)
GPIO29 (using soft-
strap)
Suspend
Low
Low
Low
14
High-Z
High
High-Z
High
High-Z
Defined
High-Z
Defined
High-Z
Processor Interface
PROCPWRGD Processor Low High High High Off Off
SMBus Interface
SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined Defined
Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations
(Sheet 2 of 6)
Signal Name
Power
Plane
During
Reset
1
Immediately
after Reset
1
C-x
states
S0/S1 S3 S4/S5