Intel 6 SERIES CHIPSET - DATASHEET 01-2011

PCH Pin States
96 Datasheet
FRAME# Core High-Z High-Z High-Z Off Off
GNT0#, GNT[3:1]#7/
GPIO[55, 53, 51]
Core High High High Off Off
IRDY#, TRDY# Core High-Z High-Z High-Z Off Off
PAR Core Low Low Low Off Off
PCIRST# Suspend Low High High Low Low
PERR# Core High-Z High-Z High-Z Off Off
PLOCK# Core High-Z High-Z High-Z Off Off
STOP# Core High-Z High-Z High-Z Off Off
LPC/FWH Interface
LAD[3:0] / FWH[3:0] Core High High High Off Off
LFRAME# / FWH[4] Core High High High Off Off
INIT3_3V#
7
Core High High High Off Off
SATA Interface
SATA[5:0]TXP,
SATA[5:0]TXN
Core High-Z High-Z Defined Off Off
SATALED# Core High-Z High-Z Defined Off Off
SATAICOMPO Core High High Defined Off Off
SCLOCK/GPIO22 Core High-Z (Input) High-Z (Input) Defined Off Off
SLOAD/GPIO38 Core High-Z (Input) High-Z (Input) Defined Off Off
SDATAOUT[1:0]/
GPIO[48,39]
Core High-Z High-Z High-Z Off Off
SATA3RBIAS Core
Terminated to
Vss
Terminated to
Vss
Terminated
to Vss
Off Off
SATA3ICOMPO Core High-Z High-Z High-Z Off Off
SATA3RCOMPO Core High-Z High-Z High-Z Off Off
Interrupts
PIRQ[A:D]# Core High-Z High-Z High-Z Off Off
PIRQ[H:E]# /
GPIO[5:2]
Core High-Z (Input) High-Z (Input) Defined Off Off
SERIRQ Core High-Z High-Z High-Z Off Off
USB Interface
USB[13:0][P,N] Suspend Low Low Defined Defined Defined
USBRBIAS Suspend High-Z High-Z High High High
Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations
(Sheet 2 of 6)
Signal Name
Power
Plane
During
Reset
1
Immediately
after Reset
1
S0/S1 S3 S4/S5