Datasheet 97
PCH Pin States
Power Management
LAN_PHY_PWR_CTRL
10
/
GPIO12
Suspend Low Low Defined Defined Defined
PLTRST# Suspend Low High High Low Low
SLP_A#
5
Suspend Low High High Defined Defined
SLP_S3# Suspend Low High High Low Low
SLP_S4# Suspend Low High High High Defined
SLP_S5#/GPIO63 Suspend Low High High High Defined
2
SUS_STAT#/GPIO61 Suspend Low High High Low Low
SUSCLK/GPIO62 Suspend Low Running
DRAMPWROK Suspend Low High-Z High-Z High-Z Low
PMSYNCH Core Low Low Defined Off Off
STP_PCI#/GPIO34 Core High-Z (Input) High-Z (Input) Defined Off Off
SLP_LAN#/GPIO29
8
SLP_LAN# (using soft-
strap)
GPIO29 (using soft-
strap)
Suspend
Low
High-Z
Low
8
High-Z
High
High-Z
Defined
High-Z
Defined
High-Z
Processor Interface
PROCPWRGD Processor Low High High Off Off
SMBus Interface
SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined
System Management Interface
SML0ALERT# / GPIO60 Suspend High-Z High-Z
11
Defined Defined Defined
SML0DATA Suspend High-Z High-Z Defined Defined Defined
SML0CLK Suspend High-Z High-Z Defined Defined Defined
SML1CLK/GPIO58 Suspend High-Z High-Z Defined Defined Defined
SML1ALERT#/PCHHOT#/
GPIO74
Suspend High-Z High-Z Defined Defined Defined
SML1DATA/GPIO75 Suspend High-Z High-Z Defined Defined Defined
Miscellaneous Signals
SPKR
7
Core Low Low Defined Off Off
JTAG_TDO Suspend High-Z High-Z High-Z High-Z High-Z
GPIO24 /
PROC_MISSING
Suspend Low Low Defined Defined Defined
Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations
(Sheet 3 of 6)
Signal Name
Power
Plane
During
Reset
1
Immediately
after Reset
1
S0/S1 S3 S4/S5
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