Serial Peripheral Interface (SPI)
810 Datasheet
78h–7Bh FPR1 Flash Protected Range 1 00000000h
7Ch–7Fh FPR2 Flash Protected Range 2 00000000h
80–83h FPR3 Flash Protected Range 3 00000000h
84h–87h FPR4 Flash Protected Range 4 00000000h
88h–8Fh — Reserved —
90h SSFSTS Software Sequencing Flash Status 00h
91h–93h SSFCTL Software Sequencing Flash Control 0000h
94h–95h PREOP Prefix Opcode Configuration 0000h
96h–97h OPTYPE Opcode Type Configuration 0000h
98h–9Fh OPMENU Opcode Menu Configuration
00000000
00000000h
A0h BBAR BIOS Base Address Configuration 00000000h
B0h–B3h FDOC Flash Descriptor Observability Control 00000000h
B4h–B7h FDOD Flash Descriptor Observability Data 00000000h
B8h–C3h — Reserved —
C0h–C3h AFC Additional Flash Control 00000000h
C4–C7h LVSCC Host Lower Vendor Specific Component Capabilities 00000000h
C8–C11h UVSCC Host Upper Vendor Specific Component Capabilities 00000000h
D0–D3h FPB Flash Partition Boundary 00000000h
F0–F3h SRDL Soft Reset Data Lock 00000000h
F4–F7h SRDC Soft Reset Data Control 00000000h
F8–FBh SRD Soft Reset Data 00000000h
Table 21-1. Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers) (Sheet 2 of 2)
SPIBAR +
Offset
Mnemonic Register Name Default
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