Datasheet 811
Serial Peripheral Interface (SPI)
21.1.1 BFPR –BIOS Flash Primary Region Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 00h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
21.1.2 HSFS—Hardware Sequencing Flash Status Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 04h Attribute: RO, R/WC, R/W
Default Value: 0000h Size: 16 bits
Bit Description
31:29 Reserved
28:16
BIOS Flash Primary Region Limit (PRL) — RO. This specifies address bits 24:12 for
the Primary Region Limit.
The value in this register loaded from the contents in the Flash
Descriptor.FLREG1.Region Limit
15:13 Reserved
12:0
BIOS Flash Primary Region Base (PRB) — RO. This specifies address bits 24:12 for
the Primary Region Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Base
Bit Description
15
Flash Configuration Lock-Down (FLOCKDN) — R/W/L. When set to 1, those Flash
Program Registers that are locked down by this FLOCKDN bit cannot be written. Once
set to 1, this bit can only be cleared by a hardware reset due to a global reset or host
partition reset in an Intel
®
ME enabled system.
14
Flash Descriptor Valid (FDV) — RO. This bit is set to a 1 if the Flash Controller read
the correct Flash Descriptor Signature.
If the Flash Descriptor Valid bit is not 1, software cannot use the Hardware Sequencing
registers, but must use the software sequencing registers. Any attempt to use the
Hardware Sequencing registers will result in the FCERR bit being set.
13
Flash Descriptor Override Pin-Strap Status (FDOPSS) — RO. This bit indicates the
condition of the Flash Descriptor Security Override / Intel ME Debug Mode Pin-Strap.
0 = The Flash Descriptor Security Override / Intel ME Debug Mode strap is set using
external pull-up on HDA_SDO
1 = No override
12:6 Reserved
5
SPI Cycle In Progress (SCIP)— RO. Hardware sets this bit when software sets the
Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit
remains set until the cycle completes on the SPI interface. Hardware automatically sets
and clears this bit so that software can determine when read data is valid and/or when
it is safe to begin programming the next command. Software must only program the
next command when this bit is 0.
NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing
is being used.
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