Intel 6 SERIES CHIPSET - DATASHEET 01-2011

DMI-To-PCI Bridge (D30:F0)117

PCI Legacy Mode117

PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7)118

Interrupt Generation118

MSI Versus PCI IRQ Actions118

Generation of SERR# to Platform120

Gigabit Ethernet Controller (B0:D25:F0)122

LPC Bridge (with System and Management Functions) (D31:F0)129

DMA Operation (D31:F0)134

Lpc Dma137

8254 Timers (D31:F0)140

8259 Interrupt Controllers (PIC) (D31:F0)143

Configuration Bits Reset by RTCRST# Assertion157

State Transition Rules for the PCH162

Causes of SMI and SCI164

Transitions Due to Power Button173

Causes of Host and Global Resets181

System Management (D31:F0)182

TCO Legacy/Compatible Mode Smbus Configuration184

Event Transitions that Cause Messages184

Advanced TCO Mode185

General Purpose I/O (D31:F0)186

SATA Host Controller (D31:F2, F5)189

High Precision Event Timers200

USB EHCI Host Controllers (D29:F0 and D26:F0)204

C Block Read218

Slave Write Registers223

Command Types223

Data Values for Slave Read Registers225

Block Read Command - Byte Definition232

Region Size Versus Erase Granularity of Flash Components244

Flash Descriptor Sections245

Region Access Control Table246

Hardware Sequencing Commands and Opcode Requirements249

Flash Protection Mechanism Summary251

Recommended Pinout for 8-Pin Serial Flash Device252

Recommended Pinout for 16-Pin Serial Flash Device252

Analog Port Characteristics254

LVDS Signals and Swing Voltage256

LVDS Clock and Data Relationship256

Panel Power Sequencing257

HDMI Overview258

DP Overview259

PCH Supported Audio Formats over HDMI and Displayport260

SDVO Conceptual Block Diagram261

PCH Digital Port Pin Mapping262

Display Co-Existence Table263

Virtualization Support for High Precision Event Timer (HPET)265

Desktop PCH Ballout (Top View - Upper Left)268

Desktop PCH Ballout (Top View - Lower Left)269

Desktop PCH Ballout (Top View - Upper Right)270

Desktop PCH Ballout (Top View - Lower Right)271

Desktop PCH Ballout by Signal Name272

Mobile PCH Ballout (Top View - Upper Left)280

Mobile PCH Ballout (Top View - Lower Left)281

Mobile PCH Ballout (Top View - Upper Right)282

Mobile PCH Ballout (Top View - Lower Right)283

Mobile PCH Ballout by Signal Name284

Desktop PCH Package Drawing294

Mobile PCH Package Drawing296

Storage Conditions297

Mobile Thermal Design Power298

PCH Absolute Maximum Ratings298

PCH Power Supply Range299

DC Characteristic Input Signal Association302

DC Input Characteristics304

DC Characteristic Output Signal Association307

DC Output Characteristics309

Other DC Characteristics311

Signal Groups312

CRT DAC Signal Group DC Characteristics: Functional Operating Range312

(Vccadac = 3.3 V ±5%)312

LVDS Interface: Functional Operating Range (Vccalvds = 1.8 V ±5%)313

Display Port Auxiliary Signal Group DC Characteristics313

PCI Express* Interface Timings314

HDMI Interface Timings (Ddp[D:b][3:0])Timings315

SDVO Interface Timings315

Displayport Interface Timings (DDP[D:B][3:0])316

Displayport aux Interface317

DDC Characteristics317

LVDS Interface AC Characteristics at Various Frequencies318

CRT DAC AC Characteristics320

Clock Timings320

PCI Interface Timing324

Universal Serial Bus Timing325

SATA Interface Timings326

Smbus and Smlink Timing327

LPC Timing328

Miscellaneous Timings328

High Definition Audio Timing328

SPI Timings (20 Mhz)329

SPI Timings (33 Mhz)329

SPI Timings (50 Mhz)330

Controller Link Receive Timings330

Power Sequencing and Reset Signal Timings331

G3 W/Rtc Loss to S4/S5 (with Deep S4/S5 Support) Timing Diagram334

G3 W/Rtc Loss to S4/S5 (Without Deep S4/S5 Support) Timing Diagram334

S5 to S0 Timing Diagram335

S3/M3 to S0 Timing Diagram336

S5/Moff - S5/M3 Timing Diagram336

S0 to S5 Timing Diagram337

S4/S5 to Deep S4/S5 to G3 W/ RTC Loss Timing Diagram338

DRAMPWROK Timing Diagram338

Clock Cycle Time339

Transmitting Position (Data to Strobe)339

Clock Timing339

Setup and Hold Times340

Float Delay340

Pulse Width340

Valid Delay from Rising Clock Edge340

Output Enable Delay341

USB Rise and Fall Times341

High Definition Audio Input and Output Timings343

Dual Channel Interface Timings344

LVDS Load and Transition Times344

Transmitting Position (Data to Strobe)345

PCI Express Transmitter Eye345

PCI Express Receiver Eye346

Measurement Points for Differential Waveforms347

PCH Test Load348

Controller Link Receive Timings348

Controller Link Receive Slew Rate348

PCI Devices and Functions350

Address Map351

Fixed I/O Ranges Decoded by Intel352

Pch352

Variable I/O Decode Ranges354

Memory Decode Ranges from Processor Perspective355

Chipset Configuration Register Memory Map (Memory Space)359

PCI Bridge Register Address Map (PCI-PCI-D30:F0)415

Gigabit LAN Configuration Registers Address Map433

(Gigabit LAN -D25:F0)433

LPC Interface PCI Register Address Map (LPC I/F-D31:F0)447

LPC Interface Bridge Registers (D31:F0)447

DMA Registers474

PIC Registers485

APIC Direct Registers493

APIC Indirect Registers493

RTC I/O Registers498

RTC (Standard) RAM Bank499

Processor Interface PCI Register Address Map503

Power Management PCI Register Address Map (PM-D31:F0)506

APM Register Map515

ACPI and Legacy I/O Register Map516

TCO I/O Register Address Map534

Registers to Control GPIO Address Map541

SATA Controller PCI Register Address Map (SATA-D31:F2)551

When Sub Class Code Register (D31:F2:Offset 0Ah) = 01H555

Bus Master IDE I/O Register Address Map579

AHCI Register Address Map588

Generic Host Controller Register Address Map589

Port [5:0] DMA Register Address Map599

SATA Controller PCI Register Address Map (SATA-D31:F5)617

Bus Master IDE I/O Register Address Map633

USB EHCI PCI Register Address Map (USB EHCI-D29:F0, D26:F0)641

Enhanced Host Controller Capability Registers661

Enhanced Host Controller Operational Register Address Map664

Debug Port Register Address Map678

Configuration Default733

Configuration Data Structure733

Smbus Controller PCI Register Address Map (Smbus-D31:F3)739

Smbus I/O and Memory Mapped I/O Register Address Map746

PCI Express* Configuration Registers Address Map757

(PCI Express*-D28:F0/F1/F2/F3/F4/F5/F6/F7)757

Memory-Mapped Registers799

Serial Peripheral Interface (SPI) Register Address Map809

(SPI Memory Mapped Configuration Registers)809

Gigabit LAN SPI Flash Program Register Address Map832

(Gbe LAN Memory Mapped Configuration Registers)832

Thermal Sensor Register Address Map845

Thermal Memory Mapped Configuration Register Address Map854

Intel (MEI - D22:F0)867

MEI Configuration Registers Address Map867

MEI1 Configuration Registers Address Map879

(Mei -D22:F1)879

MEI MMIO Register Address Map (VE - D23:F0)888

MEI MMIO Register Address Map (VE - D23:F0)891

IDE Function for Remote Boot and Installations PT IDER Register Address Map894

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 808

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