Datasheet 475
LPC Interface Bridge Registers (D31:F0)
13.2.1 DMABASE_CA—DMA Base and Current Address Registers
I/O Address: Ch. #0 = 00h; Ch. #1 = 02h Attribute: R/W
Ch. #2 = 04h; Ch. #3 = 06h Size: 16 bit (per channel),
Ch. #5 = C4h Ch. #6 = C8h but accessed in two 8-bit
Ch. #7 = CCh; quantities
Default Value: Undefined
Lockable: No Power Well: Core
CEh CFh
Channel 7 DMA Base & Current Count
Undefined R/W
D0h D1h
Channel 4–7 DMA Command
Undefined WO
Channel 4–7 DMA Status
Undefined RO
D4h D5h
Channel 4–7 DMA Write Single Mask
000001XXb WO
D6h D7h
Channel 4–7 DMA Channel Mode
000000XXb WO
D8h D9h
Channel 4–7 DMA Clear Byte Pointer
Undefined WO
DAh DBh
Channel 4–7 DMA Master Clear
Undefined WO
DCh DDh
Channel 4–7 DMA Clear Mask
Undefined WO
DEh DFh
Channel 4–7 DMA Write All Mask
0Fh R/W
Table 13-2. DMA Registers (Sheet 2 of 2)
Port Alias Register Name Default Type
Bit Description
15:0
Base and Current Address — R/W. This register determines the address for the
transfers to be performed. The address specified points to two separate registers. On
writes, the value is stored in the Base Address register and copied to the Current
Address register. On reads, the value is returned from the Current Address register.
The address increments/decrements in the Current Address register after each transfer,
depending on the mode of the transfer. If the channel is in auto-initialize mode, the
Current Address register will be reloaded from the Base Address register after a
terminal count is generated.
For transfers to/from a 16-bit slave (channels 5–7), the address is shifted left one bit
location. Bit 15 will be shifted into Bit 16.
The register is accessed in 8 bit quantities. The byte is pointed to by the current byte
pointer flip/flop. Before accessing an address register, the byte pointer flip/flop should
be cleared to ensure that the low byte is accessed first.
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