Datasheet 169
Functional Description
NOTES:
1. This column represents what the PCH would honor as wake events but there may be
enabling dependencies on the device side which are not enabled after a power loss.
2. Reset Types include: Power Button override, Intel ME initiated power button override, Intel
ME initiated host partition reset with power down, Intel ME Watchdog Timer, SMBus
unconditional power down, processor thermal trip, PCH catastrophic temperature event.
3. When the WAKE# pin is active and the PCI Express device is enabled to wake the system,
the PCH will wake the platform.
4. SATA can only trigger a wake event in S1, but if PME is asserted prior to S3/S4/S5 entry
and software does not clear the PME_B0_STS, a wake event would still result.
Intel
®
High
Definition Audio
Event sets PME_B0_STS bit;
PM_B0_EN must be enabled.
Can not wake from S5 state if
it was entered due to power
failure or power button
override.
YY
Primary PME#
PME_B0_EN bit in GPE0_EN
register.
YY
Secondary PME#
Set PME_EN bit in GPE0_EN
register.
YY
PCI_EXP_WAKE# PCI_EXP_WAKE bit. (Note 3) Y Y
SATA
Set PME_EN bit in GPE0_EN
register. (Note 4)
S1 S1
PCI_EXP PME
Message
Must use the PCI Express*
WAKE# pin rather than
messages for wake from S3,
S4, or S5.
S1 S1
SMBALERT#
Always enabled as Wake
event.
YYY
SMBus Slave
Wake Message
(01h)
Wake/SMI# command always
enabled as a Wake event.
NOTE: SMBus Slave Message
can wake the system
from S1–S5, as well as
from S5 due to Power
Button Override.
YYY
SMBus Host
Notify message
received
HOST_NOTIFY_WKEN bit
SMBus Slave Command
register. Reported in the
SMB_WAK_STS bit in the
GPEO_STS register.
YYY
Intel
®
ME Non-
Maskable Wake
Always enabled as a wake
event.
YYY
Integrated WOL
Enable Override
WOL Enable Override bit (in
Configuration Space).
Y Y Y
Table 5-29. Causes of Wake Events (Sheet 2 of 2)
Cause How Enabled
Wake from
S1, Sx
Wake from
Deep S4/S5
Wake from
S1, Sx After
Power Loss
(Note 1)
Wake from
“Reset”
Types
(Note 2)
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