Intel 6 SERIES CHIPSET - DATASHEET 01-2011

24 Datasheet
19.1.41MA—Message Signaled Interrupt Message Address
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)............................784
19.1.42MD—Message Signaled Interrupt Message Data Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................784
19.1.43SVCAP—Subsystem Vendor Capability Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................784
19.1.44SVID—Subsystem Vendor Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................784
19.1.45PMCAP—Power Management Capability Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................785
19.1.46PMC—PCI Power Management Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................785
19.1.47PMCS—PCI Power Management Control and Status
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)............................786
19.1.48MPC2—Miscellaneous Port Configuration Register 2
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................787
19.1.49MPC—Miscellaneous Port Configuration Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................788
19.1.50SMSCS—SMI/SCI Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................790
19.1.51RPDCGEN—Root Port Dynamic Clock Gating Enable
(PCI Express—D28:F0/F1/F2/F3/F4/F5/F6/F7)..........................................791
19.1.52PECR1—PCI Express* Configuration Register 1
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................791
19.1.53PECR3—PCI Express* Configuration Register 3
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................792
19.1.54UES—Uncorrectable Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................793
19.1.55UEM—Uncorrectable Error Mask
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................794
19.1.56UEV — Uncorrectable Error Severity
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................795
19.1.57CES — Correctable Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................796
19.1.58CEM — Correctable Error Mask Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................796
19.1.59AECC — Advanced Error Capabilities and Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................797
19.1.60RES — Root Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................797
19.1.61PECR2 — PCI Express* Configuration Register 2
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................798
19.1.62PEETM — PCI Express* Extended Test Mode Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................798
19.1.63PEC1 — PCI Express* Configuration Register 1
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ........................................798
20 High Precision Event Timer Registers.....................................................................799
20.1 Memory Mapped Registers ................................................................................799
20.1.1 GCAP_ID—General Capabilities and Identification Register .........................801
20.1.2 GEN_CONF—General Configuration Register.............................................801
20.1.3 GINTR_STA—General Interrupt Status Register.........................................802
20.1.4 MAIN_CNT—Main Counter Value Register.................................................802
20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register .....................803
20.1.6 TIMn_COMP—Timer n Comparator Value Register .....................................806
20.1.7 TIMERn_PROCMSG_ROUT—Timer n Processor Message Interrupt Rout Register .
807
21 Serial Peripheral Interface (SPI) ...........................................................................809
21.1 Serial Peripheral Interface Memory Mapped Configuration Registers........................809
21.1.1 BFPR –BIOS Flash Primary Region Register
(SPI Memory Mapped Configuration Registers)..........................................811
21.1.2 HSFS—Hardware Sequencing Flash Status Register
(SPI Memory Mapped Configuration Registers)..........................................811
21.1.3 HSFC—Hardware Sequencing Flash Control Register
(SPI Memory Mapped Configuration Registers)..........................................813