Datasheet 247
Functional Description
5.24.3 Flash Access
There are two types of flash accesses:
Direct Access:
• Masters are allowed to do direct read only of their primary region
— Gigabit Ethernet region can only be directly accessed by the Gigabit Ethernet
controller. Gigabit Ethernet software must use Program Registers to access the
Gigabit Ethernet region.
• Master's Host or Management Engine virtual read address is converted into the SPI
Flash Linear Address (FLA) using the Flash Descriptor Region Base/Limit registers
Program Register Access:
• Program Register Accesses are not allowed to cross a 4 KB boundary and can not
issue a command that might extend across two components
• Software programs the FLA corresponding to the region desired
— Software must read the devices Primary Region Base/Limit address to create a
FLA.
5.24.3.1 Direct Access Security
• Requester ID of the device must match that of the primary Requester ID in the
Master Section
• Calculated Flash Linear Address must fall between primary region base/limit
• Direct Write not allowed
• Direct Read Cache contents are reset to 0's on a read from a different master
— Supports the same cache flush mechanism in ICH7 which includes Program
Register Writes
5.24.3.2 Register Access Security
• Only primary region masters can access the registers
Note: Processor running Gigabit Ethernet software can access Gigabit Ethernet registers
• Masters are only allowed to read or write those regions they have read/write
permission
• Using the Flash Region Access Permissions, one master can give another master
read/write permissions to their area
• Using the five Protected Range registers, each master can add separate read/write
protection above that granted in the Flash Descriptor for their own accesses
— Example: BIOS may want to protect different regions of BIOS from being
erased
— Ranges can extend across region boundaries
5.24.4 Serial Flash Device Compatibility Requirements
A variety of serial flash devices exist in the market. For a serial flash device to be
compatible with the PCH SPI bus, it must meet the minimum requirements detailed in
the following sections.
Note: All PCH platforms have require Intel Management engine Firmware.
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