Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Electrical Characteristics
332 Datasheet
NOTES:
t225 VccRTC active to VccDSW3_3 active 0 — ms 1, 12 8-2
t226
RTCRST# deassertion to RSMRST#
deassertion
20 — ns 8-2
t227 VccSus active to VccASW active 0 — ms 1
t229 VccASW active to Vcc active 0 — ms
t230 APWROK high to PWROK high 0 — ms
t231 PWROK low to Vcc falling 40 — ns
13, 14,
15
t232 APWROK falling to VccASW falling 40 — ns 15
t233
SLP_S3# assertion to VccCore rail
falling
5 — µs 13, 14
t234 DPWROK falling to VccDSW rail falling 40 ns 8-7
t235
RSMRST# assertion to VccSUS rail
falling
40 — ns
1, 14,
15
8-7
t236
RTCRST# deassertion to VccRTC rail
falling
0—ms 8-7
t237
SLP_LAN# (or LANPHYPC) rising to
Intel LAN Phy power high and stable
—20ms
t238
DPWROK falling to any of VccDSW,
VccSUS, VccASW, VccASW3_3, or Vcc
falling
40 — ns
1, 13,
14, 15
t239 V5REF_Sus active to VccSus3_3 active 0 — ms 16
t240 V5REF active to Vcc3_3 active
See
note
15
—ms16
t241
VccSus supplies active to Vcc supplies
active
0 — ms 1, 13
t242 HDA_RST# active low pulse width 1 — s
t244
VccSus active to SLP_S5#, SLP_S4#,
SLP_S3#, SUS_STAT#, PLTRST# and
PCIRST# valid
—50ns20
t246
S4 Wake Event to SLP_S4# inactive
(S4 Wake)
See Note Below 5
t247
S3 Wake Event to SLP_S3# inactive
(S3 Wake)
See Note Below 6
t251
RSMRST# deassertion to APWROK
assertion
0—ms
t252
THRMTRIP# active to SLP_S3#,
SLP_S4#, SLP_S5# active
—175ns
t253
RSMRST# rising edge transition from
20% to 80%
—50s
t254 RSMRST# falling edge transition — 50 µs 18, 19
Table 8-36. Power Sequencing and Reset Signal Timings (Sheet 2 of 2)
Sym Parameter Min Max Units Notes Fig