Datasheet 353
Register and Memory Mapping
NOTE:
1. A read to this address will subtractively go to PCI, where it will master abort.
89h–8Bh DMA Controller DMA Controller DMA
8Ch–8Eh DMA Controller DMA Controller and LPC or PCI DMA
08Fh DMA Controller DMA Controller DMA
90h–91h DMA Controller DMA Controller DMA
92h Reset Generator Reset Generator Processor I/F
93h–9Fh DMA Controller DMA Controller DMA
A0h–A1h Interrupt Controller Interrupt Controller Interrupt
A4h–A5h Interrupt Controller Interrupt Controller Interrupt
A8h–A9h Interrupt Controller Interrupt Controller Interrupt
ACh–ADh Interrupt Controller Interrupt Controller Interrupt
B0h–B1h Interrupt Controller Interrupt Controller Interrupt
B2h–B3h Power Management Power Management
Power
Management
B4h–B5h Interrupt Controller Interrupt Controller Interrupt
B8h–B9h Interrupt Controller Interrupt Controller Interrupt
BCh–BDh Interrupt Controller Interrupt Controller Interrupt
C0h–D1h DMA Controller DMA Controller DMA
D2h–DDh RESERVED DMA Controller DMA
DEh–DFh DMA Controller DMA Controller DMA
F0h PCI and Master Abort
1
FERR#/IGNNE# / Interrupt
Controller
Processor I/F
170h–177h SATA Controller or PCI SATA Controller or PCI
Forwarded to
SATA
1F0h–1F7h SATA Controller or PCI SATA Controller or PCI
Forwarded to
SATA
376h SATA Controller or PCI SATA Controller or PCI
Forwarded to
SATA
3F6h SATA Controller or PCI SATA Controller or PCI
Forwarded to
SATA
4D0h–4D1h Interrupt Controller Interrupt Controller Interrupt
CF9h Reset Generator Reset Generator Processor I/F
Table 9-2. Fixed I/O Ranges Decoded by Intel
®
PCH (Sheet 2 of 2)
I/O
Address
Read Target Write Target Internal Unit
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