Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 365

Datasheet 365
Chipset Configuration Registers
10.1.4 FLRSTAT—FLR Pending Status Register
Offset Address: 0408–040Bh Attribute: RO
Default Value: 00000000h Size: 32-bit
10.1.5 CIR2—Chipset Initialization Register 2
Offset Address: 0900–0901h Attribute: R/W
Default Value: 0000h Size: 16-bit
10:8
Root Port 3 Function Number (RP3FN) — R/WO. These bits set the function
number for PCI Express Root Port 3. This root port function number must be a
unique value from the other root port function numbers
7
Root Port 2 Config Hide (RP2CH) — R/W. This bit is used to hide the root port
and any devices behind it from being discovered by the OS. When set to 1, the root
port will not claim any downstream configuration transactions.
6:4
Root Port 2 Function Number (RP2FN) — R/WO. These bits set the function
number for PCI Express Root Port 2. This root port function number must be a
unique value from the other root port function numbers
3
Root Port 1 Config Hide (RP1CH) — R/W. This bit is used to hide the root port
and any devices behind it from being discovered by the OS. When set to 1, the root
port will not claim any downstream configuration transactions.
2:0
Root Port 1 Function Number (RP1FN) — R/WO. These bits set the function
number for PCI Express Root Port 1. This root port function number must be a
unique value from the other root port function numbers
Bit Description
Bit Description
31:17 Reserved.
16
FLR Pending Status for D29:F0, EHCI #1 — RO.
0 = Function Level Reset is not pending.
1 = Function Level Reset is pending.
15
FLR Pending Status for D26:F0, EHCI #2 — RO.
0 = Function Level Reset is not pending.
1 = Function Level Reset is pending.
10:9 Reserved
8
FLR Pending Status for D26:F0, EHCI#2 — RO.
0 = Function Level Reset is not pending.
1 = Function Level Reset is pending.
7:0 Reserved.
Bit Description
15:0 CIR2 Field 1 — R/W. BIOS must program this field to 4000h.