Datasheet 401
Chipset Configuration Registers
10.1.72 GCS—General Control and Status Register
Offset Address: 3410–3413h Attribute: R/W, R/WLO
Default Value: 00000yy0h (yy = xx0000x0b)Size: 32-bit
Bit Description
31:13 Reserved.
12
Function Level Reset Capability Structure Select (FLRCSSEL) — R/W.
0 = Function Level Reset (FLR) will utilize the standard capability structure with
unique capability ID assigned by PCISIG.
1 = Vendor Specific Capability Structure is selected for FLR.
11:10
Boot BIOS Straps (BBS) — R/W. This field determines the destination of accesses
to the BIOS memory range. The default values for these bits represent the strap
values of GNT1#/GPIO51 (bit 11) at the rising edge of PWROK and SATA1GP/GPIO19
(bit 10) at the rising edge of PWROK.
When PCI is selected, the top 16 MB of memory below 4 GB (FF00_0000h to
FFFF_FFFFh) is accepted by the primary side of the PCI P2P bridge and forwarded to
the PCI bus. This allows systems with corrupted or unprogrammed flash to boot from
a PCI device. The PCI-to-PCI bridge Memory Space Enable bit does not need to be set
(nor any other bits) in order for these cycles to go to PCI. Note that BIOS decode
range bits and the other BIOS protection bits have no effect when PCI is selected.
This functionality is intended for debug/testing only.
When SPI or LPC is selected, the range that is decoded is further qualified by other
configuration bits described in the respective sections.
The value in this field can be overwritten by software as long as the BIOS Interface
Lock-Down (bit 0) is not set.
NOTE: Booting to PCI is intended for debug/testing only. Boot BIOS Destination
Select to LPC/PCI by functional strap or using Boot BIOS Destination Bit will
not affect SPI accesses initiated by Intel
®
Management Engine or Integrated
GbE LAN.
9
Server Error Reporting Mode (SERM) — R/W.
0 = The PCH is the final target of all errors. The processor sends a messages to the
PCH for the purpose of generating NMI.
1 = The processor is the final target of all errors from PCI Express* and DMI. In this
mode, if the PCH detects a fatal, non-fatal, or correctable error on DMI or its
downstream ports, it sends a message to the processor. If the PCH receives an
ERR_* message from the downstream port, it sends that message to the
processor.
8:6 Reserved
5
No Reboot (NR) — R/W. This bit is set when the “No Reboot” strap (SPKR pin on the
PCH) is sampled high on PWROK. This bit may be set or cleared by software if the
strap is sampled low but may not override the strap when it indicates “No Reboot”.
0 = System will reboot upon the second timeout of the TCO timer.
1 = The TCO timer will count down and generate the SMI# on the first timeout, but
will not reboot on the second timeout.
Bits 11:10 Description
00b LPC
01b Reserved
10b PCI
11b SPI
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