PCI-to-PCI Bridge Registers (D30:F0)
424 Datasheet
11.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 28h–2Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
11.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0)
Offset Address: 2C–2Fh Attribute: R/W
Default Value: 00000000h Size: 32 bits
11.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0)
Offset Address: 34h Attribute: RO
Default Value: 50h Size: 8 bits
11.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0)
Offset Address: 3Ch–3Dh Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
31:0
Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the
prefetchable address base.
Bit Description
31:0
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the
prefetchable address limit.
Bit Description
7:0
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
capabilities list is at 50h in configuration space.
Bit Description
15:8 Interrupt Pin (IPIN) — RO. The PCI bridge does not assert an interrupt.
7:0
Interrupt Line (ILINE) — R/W. Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this register.
Since the bridge does not generate an interrupt, BIOS should program this value to FFh
as per the PCI bridge specification.
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