Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Datasheet 443
Gigabit LAN Configuration Registers
12.1.22 DR—Data Register
(Gigabit LAN—D25:F0)
Address Offset: CFh Attribute: RO
Default Value: See bit description Size: 8 bits
12.1.23 CLIST 2—Capabilities List Register 2
(Gigabit LAN—D25:F0)
Address Offset: D0h–D1h Attribute: R/WO, RO
Default Value: E005h Size: 16 bits
Function Level Reset: No (Bits 15:8 only)
12.1.24 MCTL—Message Control Register
(Gigabit LAN—D25:F0)
Address Offset: D2h–D3h Attribute: R/W, RO
Default Value: 0080h Size: 16 bits
Bit Description
7:0
Reported Data (RD) — RO. This register is used to report power consumption and
heat dissipation. This register is controlled by the Data_Select field in the PMCS (Offset
CCh, bits 12:9), and the power scale is reported in the Data_Scale field in the PMCS
(Offset CCh, bits 14:13). The data of this field is loaded from the NVM if PM is enabled
in the NVM or with a default value of 00h otherwise.
Bit Description
15:8
Next Capability (NEXT) — R/WO. Value of E0h points to the Function Level Reset
capability structure.
These bits are not reset by Function Level Reset.
7:0
Capability ID (CID) — RO. Indicates the linked list item is a Message Signaled
Interrupt Register.
Bit Description
15:8 Reserved
7
64-bit Capable (CID) — RO. Set to 1 to indicate that the GbE LAN Controller is
capable of generating 64-bit message addresses.
6:4
Multiple Message Enable (MME) — RO. Returns 000b to indicate that the GbE LAN
controller only supports a single message.
3:1
Multiple Message Capable (MMC) — RO. The GbE LAN controller does not support
multiple messages.
0
MSI Enable (MSIE) — R/W.
0 = MSI generation is disabled.
1 = The Gb LAN controller will generate MSI for interrupt assertion instead of INTx
signaling.