Datasheet 465
LPC Interface Bridge Registers (D31:F0)
13.1.28 LGMR — LPC I/F Generic Memory Range
(LPC I/F—D31:F0)
Offset Address: 98h – 9Bh Attribute: R/W
Default Value: 00000000h Size: 32 bit
Power Well: Core
13.1.29 BIOS_SEL1—BIOS Select 1 Register
(LPC I/F—D31:F0)
Offset Address: D0h–D3h Attribute: R/W, RO
Default Value: 00112233h Size: 32 bits
Bit Description
31:16
Memory Address[31:16] — R/W. This field specifies a 64 KB memory block
anywhere in the 4 GB memory space that will be decoded to LPC as standard LPC
memory cycle if enabled.
15:1 Reserved
0
LPC Memory Range Decode Enable — R/W. When this bit is set to 1, then the range
specified in bits 31:16 of this register is enabled for decoding to LPC.
Bit Description
31:28
BIOS_F8_IDSEL — RO. IDSEL for two 512-KB BIOS memory ranges and one 128-KB
memory range. This field is fixed at 0000. The IDSEL programmed in this field
addresses the following memory ranges:
FFF8 0000h – FFFF FFFFh
FFB8 0000h – FFBF FFFFh
000E 0000h – 000F FFFFh
27:24
BIOS_F0_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
FFF0 0000h – FFF7 FFFFh
FFB0 0000h – FFB7 FFFFh
23:20
BIOS_E8_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
FFE8 0000h – FFEF FFFFh
FFA8 0000h – FFAF FFFFh
19:16
BIOS_E0_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
FFE0 0000h – FFE7 FFFFh
FFA0 0000h – FFA7 FFFFh
15:12
BIOS_D8_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
FFD8 0000h – FFDF FFFFh
FF98 0000h – FF9F FFFFh
11:8
BIOS_D0_IDSEL — R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
FFD0 0000h – FFD7 FFFFh
FF90 0000h – FF97 FFFFh
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