LPC Interface Bridge Registers (D31:F0)
488 Datasheet
13.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register
Offset Address: A1h Attribute: WO
Default Value: All bits undefined Size: 8 bits
13.4.6 ICW4—Initialization Command Word 4 Register
Offset Address: Master Controller – 021h Attribute:WO
Slave Controller
– 0A1h Size: 8 bits
Default Value: 01h
Bit Description
7:3 0 = These bits must be programmed to 0.
2:0
Slave Identification Code — WO. These bits are compared against the slave
identification code broadcast by the master controller from the trailing edge of the first
internal INTA# pulse to the trailing edge of the second internal INTA# pulse. These bits
must be programmed to 02h to match the code broadcast by the master controller.
When 02h is broadcast by the master controller during the INTA# sequence, the slave
controller assumes responsibility for broadcasting the interrupt vector.
Bit Description
7:5 0 = These bits must be programmed to 0.
4
Special Fully Nested Mode (SFNM) — WO.
0 = Should normally be disabled by writing a 0 to this bit.
1 = Special fully nested mode is programmed.
3
Buffered Mode (BUF) — WO.
0 = Must be programmed to 0 for the PCH. This is non-buffered mode.
2
Master/Slave in Buffered Mode — WO. Not used.
0 = Should always be programmed to 0.
1
Automatic End of Interrupt (AEOI) — WO.
0 = This bit should normally be programmed to 0. This is the normal end of interrupt.
1 = Automatic End of Interrupt (AEOI) mode is programmed.
0
Microprocessor Mode — WO.
1 = Must be programmed to 1 to indicate that the controller is operating in an Intel
Architecture-based system.
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