Datasheet 49
Introduction
System Management Bus (SMBus 2.0)
The PCH contains an SMBus Host interface that allows the processor to communicate
with SMBus slaves. This interface is compatible with most I
2
C devices. Special I
2
C
commands are implemented.
The PCH’s SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the PCH supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports
eight command protocols of the SMBus interface (see System Management Bus
(SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
The PCH’s SMBus also implements hardware-based Packet Error Checking for data
robustness and the Address Resolution Protocol (ARP) to dynamically provide address
to all SMBus devices.
Intel
®
High Definition Audio Controller
The Intel
®
High Definition Audio Specification defines a digital interface that can be
used to attach different types of codecs, such as audio and modem codecs. The PCH
Intel
®
HD Audio controller supports up to 4 codecs. The link can operate at either 3.3 V
or 1.5 V.
With the support of multi-channel audio stream, 32-bit sample depth, and sample rate
up to 192 kHz, the Intel HD Audio controller provides audio quality that can deliver CE
levels of audio experience. On the input side, the PCH adds support for an array of
microphones.
Intel
®
Virtualization Technology for Directed I/O (Intel VT-d)
The PCH provides hardware support for implementation of Intel Virtualization
Technology with Directed I/O (Intel
®
VT-d). Intel VT-d Technology consists of
technology components that support the virtualization of platforms based on Intel
®
Architecture processors. Intel VT-d technology enables multiple operating systems and
applications to run in independent partitions. A partition behaves like a virtual machine
(VM) and provides isolation and protection across partitions. Each partition is allocated
it’s own subset of host physical memory.
JTAG Boundary-Scan
The PCH implements the industry standard JTAG interface and enables Boundary-Scan
in place of the XOR chains used in previous generations of chipsets. Boundary-Scan can
be used to ensure device connectivity during the board manufacturing process. The
JTAG interface allows system manufacturers to improve efficiency by using industry
available tools to test the PCH on an assembled board. Since JTAG is a serial interface,
it eliminates the need to create probe points for every pin in an XOR chain. This eases
pin breakout and trace routing and simplifies the interface between the system and a
bed-of-nails tester.
Note: Contact your local Intel Field Sales Representative for additional information about
JTAG usage on the PCH.
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