Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 513

Datasheet 513
LPC Interface Bridge Registers (D31:F0)
13.8.1.6 BM_BREAK_EN Register #2(PM—D31:F0)
Offset Address: AAh Attribute: R/W, RO
Default Value: 00h Size: 8-bit
Lockable: No Usage: ACPI, Legacy
Power Well: Core
13.8.1.7 BM_BREAK_EN Register (PM—D31:F0)
Offset Address: ABh Attribute: R/W
Default Value: 00h Size: 8-bit
Lockable: No Usage: ACPI, Legacy
Power Well: Core
Bit Description
7:1 Reserved
0
SATA3 Break Enable (SATA3_BREAK_EN) — R/W.
0 = SATA3 traffic will not cause BM_STS to be set.
1 = SATA3 traffic will cause BM_STS to be set.
Bit Description
7
Storage Break Enable (STORAGE_BREAK_EN) — R/W.
0 = Serial ATA traffic will not cause BM_STS to be set.
1 = Serial ATA traffic will cause BM_STS to be set.
6
PCIE_BREAK_EN — R/W.
0 = PCI Express* traffic will not cause BM_STS to be set.
1 = PCI Express traffic will cause BM_STS to be set.
5
PCI_BREAK_EN — R/W.
0 = PCI traffic will not cause BM_STS to be set.
1 = PCI traffic will cause BM_STS to be set.
4:3 Reserved
2
EHCI_BREAK_EN — R/W.
0 = EHCI traffic will not cause BM_STS to be set.
1 = EHCI traffic will cause BM_STS to be set.
1 Reserved
0
HDA_BREAK_EN — R/W.
0 = Intel
®
High Definition Audio traffic will not cause BM_STS to be set.
1 = Intel
®
High Definition Audio traffic will cause BM_STS to be set.