Datasheet 521
LPC Interface Bridge Registers (D31:F0)
13.8.3.4 PM1_TMR—Power Management 1 Timer Register
I/O Address: PMBASE + 08h
Attribute: RO
Default Value: xx000000h Size: 32-bit
Lockable: No Usage: ACPI
Power Well: Core
Bit Description
31:24 Reserved
23:0
Timer Value (TMR_VAL) — RO. Returns the running count of the PM timer. This
counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0
during a PCI reset, and then continues counting as long as the system is in the S0
state. After an S1 state, the counter will not be reset (it will continue counting from the
last value in S0 state.
Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the
TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur
every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI
interrupt is also generated.
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