Datasheet 525
LPC Interface Bridge Registers (D31:F0)
13.8.3.6 GPE0_EN—General Purpose Event 0 Enables Register
I/O Address: PMBASE + 28h
Attribute: R/W
Default Value: 0000000000000000h Size: 64-bit
Lockable: No Usage: ACPI
Power Well: Bits 0–7, 9, 12, 14–34, 36–63 Resume,
Bits 8, 10–11, 13,35 RTC
This register is symmetrical to the General Purpose Event 0 Status Register.
Bit Description
63:36 Reserved.
35
GPIO27_EN — R/W.
0 = Disable.
1 = Enable the setting of the GPIO27_STS bit to generate a wake event/SCI/SMI#.
GPIO27 is a valid host wake event from Deep S4/S5. The wake enable configuration
persists after a G3 state.
34:32 Reserved.
31:16
GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to
cause a SCI, and/or wake event. These bits are cleared by RSMRST#.
NOTE: Mapping is as follows: bit 31 corresponds to GPIO15... and bit 16
corresponds to GPIO0.
15:14 Reserved
13
PME_B0_EN — R/W.
0 = Disable
NOTE: Enables the setting of the PME_B0_STS bit to generate a wake event and/or
an SCI or SMI#. In addition to being cleared by RTCRST# assertion, the PCH
also clears this bit due to a Power Button Override event, Intel ME Initiated
Power Button Override, Intel ME Initiated Host Reset with Power down,
SMBus unconditional power down, processor thermal trip event, or due to an
internal thermal sensor catastrophic condition.
12 Reserved
11
PME_EN — R/W.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.
PME# can be a wake event from the S1 – S4 state or from S5 (if entered using
SLP_EN, but not power button override).
In addition to being cleared by RTCRST# assertion, the PCH also clears this bit due
to a Power Button Override event, Intel ME Initiated Power Button Override, Intel
ME Initiated Host Reset with Power down, SMBus unconditional power down,
processor thermal trip event, or due to an internal thermal sensor catastrophic
condition.
10
(Desktop
Only)
Reserved
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