Datasheet 527
LPC Interface Bridge Registers (D31:F0)
13.8.3.7 SMI_EN—SMI Control and Enable Register
I/O Address: PMBASE + 30h Attribute: R/W, R/WO, WO
Default Value: 00000002h Size: 32 bit
Lockable: No Usage: ACPI or Legacy
Power Well: Core
Note: This register is symmetrical to the SMI status register.
Bit Description
31:28 Reserved
27
GPIO_UNLOCK_SMI_EN— R/WO. Setting this bit will cause the Intel
®
PCH to
generate an SMI# when the GPIO_UNLOCK_SMI_STS bit is set in the SMI_STS
register.
Once written to 1, this bit can only be cleared by PLTRST#.
26:19 Reserved
18
INTEL_USB2_EN — R/W.
0 = Disable
1 = Enables Intel-Specific EHCI SMI logic to cause SMI#.
17
LEGACY_USB2_EN — R/W.
0 = Disable
1 = Enables legacy EHCI logic to cause SMI#.
16:15 Reserved
14
PERIODIC_EN — R/W.
0 = Disable.
1 = Enables the PCH to generate an SMI# when the PERIODIC_STS bit (PMBASE +
34h, bit 14) is set in the SMI_STS register (PMBASE + 34h).
13
TCO_EN — R/W.
0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set,
SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN bit. Even
if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs.
1 = Enables the TCO logic to generate SMI#.
NOTE: This bit cannot be written once the TCO_LOCK bit is set.
12 Reserved
11
MCSMI_EN Microcontroller SMI Enable (MCSMI_EN) — R/W.
0 = Disable.
1 = Enables PCH to trap accesses to the microcontroller range (62h or 66h) and
generate an SMI#. Note that “trapped’ cycles will be claimed by the PCH on PCI,
but not forwarded to LPC.
10:8 Reserved
7
BIOS Release (BIOS_RLS) — WO.
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI software when a one is written
to this bit position by BIOS software.
NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set.
Software must take great care not to set the BIOS_RLS bit (which causes
GBL_STS to be set) if the SCI handler is not in place.
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