Datasheet 529
LPC Interface Bridge Registers (D31:F0)
13.8.3.8 SMI_STS—SMI Status Register
I/O Address: PMBASE + 34h Attribute: RO, R/WC
Default Value: 00000000h Size: 32-bit
Lockable: No Usage: ACPI or Legacy
Power Well: Core
Note: If the corresponding _EN bit is set when the _STS bit is set, the PCH will cause an SMI#
(except bits 8–10 and 12, which do not need enable bits since they are logic ORs of
other registers that have enable bits). The PCH uses the same GPE0_EN register (I/O
address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI general purpose input
events. ACPI OS assumes that it owns the entire GPE0_EN register per the ACPI
specification. Problems arise when some of the general-purpose inputs are enabled as
SMI by BIOS, and some of the general purpose inputs are enabled for SCI. In this case
ACPI OS turns off the enabled bit for any GPIx input signals that are not indicated as
SCI general-purpose events at boot, and exit from sleeping states. BIOS should define
a dummy control method which prevents the ACPI OS from clearing the SMI GPE0_EN
bits.
Bit Description
31:28 Reserved
27
GPIO_UNLOCK_SMI_STS — R/WC. This bit will be set if the GPIO registers lockdown
logic is requesting an SMI#. Writing a 1 to this bit position clears this bit to 0.
26
SPI_STS — RO. This bit will be set if the SPI logic is generating an SMI#. This bit is
read only because the sticky status and enable bits associated with this function are
located in the SPI registers.
25:22 Reserved
21
MONITOR_STS — RO. This bit will be set if the Trap/SMI logic has caused the SMI.
This will occur when the processor or a bus master accesses an assigned register (or a
sequence of accesses). See Section 10.1.30 through Section 10.1.45 for details on the
specific cause of the SMI.
20
PCI_EXP_SMI_STS — RO. PCI Express* SMI event occurred. This could be due to a
PCI Express PME event or Hot-Plug event.
19 Reserved
18
INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the
SMI status bits in the Intel-Specific EHCI SMI Status Register ANDed with the
corresponding enable bits. This bit will not be active if the enable bits are not set.
Writes to this bit will have no effect.
All integrated EHCIs are represented with this bit.
17
LEGACY_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the
SMI status bits in the EHCI Legacy Support Register ANDed with the corresponding
enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will
have no effect.
All integrated ECHIs are represented with this bit.
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