EasyManua.ls Logo

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 595

Intel 6 SERIES CHIPSET - DATASHEET 01-2011
936 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Datasheet 595
SATA Controller Registers (D31:F2)
14.4.1.5 VS—AHCI Version (D31:F2)
Address Offset: ABAR + 10h–13h Attribute: RO
Default Value: 00010300h Size: 32 bits
This register indicates the major and minor version of the AHCI specification. It is BCD
encoded. The upper two bytes represent the major version number, and the lower two
bytes represent the minor version number. Example: Version 3.12 would be
represented as 00030102h. The current version of the specification is 1.30
(00010300h).
14.4.1.6 EM_LOC—Enclosure Management Location Register (D31:F2)
Address Offset: ABAR + 1Ch–1Fh Attribute: RO
Default Value: 01600002h Size: 32 bits
This register identifies the location and size of the enclosure management message
buffer. This register is reserved if enclosure management is not supported (that is,
CAP.EMS = 0).
Bit Description
31:16 Major Version Number (MJR) — RO. Indicates the major version is 1
15:0 Minor Version Number (MNR) — RO. Indicates the minor version is 30.
Bit Description
31:16
Offset (OFST) — RO. The offset of the message buffer in Dwords from the beginning
of the ABAR.
15:0
Buffer Size (SZ) — RO. Specifies the size of the transmit message buffer area in
Dwords. The PCH SATA controller only supports transmit buffer.
A value of 0 is invalid.

Table of Contents

Related product manuals