SATA Controller Registers (D31:F2)
610 Datasheet
14.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2)
Address Offset: Port 0: ABAR + 120h Attribute: RO
Port 1: ABAR + 1A0h
Port 2: ABAR + 220h (if port available; see Section 1.3)
Port 3: ABAR + 2A0h (if port available; see Section 1.3)
Port 4: ABAR + 320h
Port 5: ABAR + 3A0h
Default Value: 0000007Fh Size: 32 bits
This is a 32-bit register that copies specific fields of the task file when FISes are
received. The FISes that contain this information are: D2H Register FIS,PIO Setup FIS
and Set Device Bits FIS
14.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2)
Address Offset: Port 0: ABAR + 124h Attribute: RO
Port 1: ABAR + 1A4h
Port 2: ABAR + 224h (if port available; see Section 1.3)
Port 3: ABAR + 2A4h (if port available; see Section 1.3)
Port 4: ABAR + 324h
Port 5: ABAR + 3A4h
Default Value: FFFFFFFFh Size: 32 bits
This is a 32-bit register which contains the initial signature of an attached device when
the first D2H Register FIS is received from that device. It is updated once after a reset
sequence.
Bit Description
31:16 Reserved
15:8 Error (ERR) — RO. Contains the latest copy of the task file error register.
7:0
Status (STS) — RO. Contains the latest copy of the task file status register. Fields of
note in this register that affect AHCI.
Bit Field Definition
7 BSY Indicates the interface is busy
6:4 N/A Not applicable
3 DRQ Indicates a data transfer is requested
2:1 N/A Not applicable
0 ERR Indicates an error during the transfer
Bit Description
31:0
Signature (SIG) — RO. Contains the signature received from a device on the first D2H
register FIS. The bit order is as follows:
Bit Field
31:24 LBA High Register
23:16 LBA Mid Register
15:8 LBA Low Register
7:0 Sector Count Register
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