Datasheet 635
SATA Controller Registers (D31:F5)
15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5)
Address Offset: Primary: BAR + 02h Attribute: R/W, R/WC, RO
Secondary: BAR + 0Ah
Default Value: 00h Size: 8 bits
15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F5)
Address Offset: Primary: BAR + 04h–07h Attribute: R/W
Secondary: BAR + 0Ch
–0Fh
Default Value: All bits undefined Size: 32 bits
Bit Description
7
PRD Interrupt Status (PRDIS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit
set.
6 Reserved.
5
Drive 0 DMA Capable — R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
drive 0 for this channel is capable of DMA transfers, and that the controller has
been initialized for optimum performance. The PCH does not use this bit. It is
intended for systems that do not attach BMIDE to the PCI bus.
4:3 Reserved.
2
Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not
disabled interrupts using the IEN bit of the Device Control Register (see chapter 5
of the Serial ATA Specification, Revision 1.0a).
1
Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the controller encounters a target abort or master abort when
transferring data on PCI.
0
Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the PCH when the last transfer for a region is performed,
where EOT for that region is set in the region descriptor. It is also cleared by the
PCH when the Start Bus Master bit (D31:F5:BAR+ 00h, bit 0) is cleared in the
Command register. When this bit is read as a 0, all data transferred from the drive
during the previous bus master command is visible in system memory, unless the
bus master command was aborted.
1 = Set by the PCH when the Start bit is written to the Command register.
Bit Description
31:2
Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits
[31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor
Table must be DWord-aligned. The Descriptor Table must not cross a 64-K boundary in
memory.
1:0 Reserved
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