EHCI Controller Registers (D29:F0, D26:F0)
668 Datasheet
16.2.2.2 USB2.0_STS—USB 2.0 Status Register
Offset: MEM_BASE + 24h–27h Attribute: R/WC, RO
Default Value: 00001000h Size: 32 bits
This register indicates pending interrupts and various states of the Host controller. The
status resulting from a transaction on the serial bus is not indicated in this register. See
the Interrupts description in section 4 of the EHCI specification for additional
information concerning USB 2.0 interrupt conditions.
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has
no effect.
Bit Description
31:16 Reserved.
15
Asynchronous Schedule Status RO. This bit reports the current real status of the
Asynchronous Schedule.
0 = Disabled. (Default)
1 = Enabled.
NOTE: The Host controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous Schedule
Enable bit (D29:F0, D26:F0:CAPLENGTH + 20h, bit 5) in the USB2.0_CMD
register. When this bit and the Asynchronous Schedule Enable bit are the same
value, the Asynchronous Schedule is either enabled (1) or disabled (0).
14
Periodic Schedule Status RO. This bit reports the current real status of the Periodic
Schedule.
0 = Disabled. (Default)
1 = Enabled.
NOTE: The Host controller is not required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule Enable bit (D29:F0,
D26:F0:CAPLENGTH + 20h, bit 4) in the USB2.0_CMD register. When this bit and
the Periodic Schedule Enable bit are the same value, the Periodic Schedule is
either enabled (1) or disabled (0).
13
Reclamation RO. This read-only status bit is used to detect an empty asynchronous
schedule. The operational model and valid transitions for this bit are described in
Section 4 of the EHCI Specification.
12
HCHalted RO.
0 = This bit is a 0 when the Run/Stop bit is a 1.
1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the
Run/Stop bit being set to 0, either by software or by the Host controller hardware
(such as, internal error). (Default)
11:6 Reserved
5
Interrupt on Async Advance — R/WC. System software can force the host controller
to issue an interrupt the next time the host controller advances the asynchronous
schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit (D29:F0,
D26:F0:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD register. This bit indicates the
assertion of that interrupt source.
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