EHCI Controller Registers (D29:F0, D26:F0)
670 Datasheet
16.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register
Offset: MEM_BASE + 28h–2Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
This register enables and disables reporting of the corresponding interrupt to the
software. When a bit is set and the corresponding interrupt is active, an interrupt is
generated to the host. Interrupt sources that are disabled in this register still appear in
the USB2.0_STS Register to allow the software to poll for events. Each interrupt enable
bit description indicates whether it is dependent on the interrupt threshold mechanism
(see Section 4 of the EHCI specification), or not.
Bit Description
31:6 Reserved.
5
Interrupt on Async Advance Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the Interrupt on Async Advance bit (D29:F0,
D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register is a 1, the host
controller will issue an interrupt at the next interrupt threshold. The interrupt is
acknowledged by software clearing the Interrupt on Async Advance bit.
4
Host System Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the Host System Error Status bit (D29:F0,
D26:F0:CAPLENGTH + 24h, bit 4) in the USB2.0_STS register is a 1, the host
controller will issue an interrupt. The interrupt is acknowledged by software clearing
the Host System Error bit.
3
Frame List Rollover Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the Frame List Rollover bit (D29:F0,
D26:F0:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register is a 1, the host
controller will issue an interrupt. The interrupt is acknowledged by software clearing
the Frame List Rollover bit.
2
Port Change Interrupt Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the Port Change Detect bit (D29:F0,
D26:F0:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is a 1, the host
controller will issue an interrupt. The interrupt is acknowledged by software clearing
the Port Change Detect bit.
1
USB Error Interrupt Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the USBERRINT bit (D29:F0, D26:F0:CAPLENGTH
+ 24h, bit 1) in the USB2.0_STS register is a 1, the host controller will issue an
interrupt at the next interrupt threshold. The interrupt is acknowledged by software
by clearing the USBERRINT bit in the USB2.0_STS register.
0
USB Interrupt Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the USBINT bit (D29:F0, D26:F0:CAPLENGTH +
24h, bit 0) in the USB2.0_STS register is a 1, the host controller will issue an
interrupt at the next interrupt threshold. The interrupt is acknowledged by software
by clearing the USBINT bit in the USB2.0_STS register.
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