Integrated Intel
®
High Definition Audio Controller Registers
698 Datasheet
17.1.1.34 DEVC—Device Control Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 78h–79h Attribute: R/W, RO
Default Value: 0800h Size: 16 bits
Function Level Reset: No (Bit 11 Only)
Bit Description
15
Initiate FLR (IF) — R/W. This bit is used to initiate FLR transition.
1 = A write of 1 initiates FLR transition. Since hardware does not respond to any cycles
until FLR completion, the read value by software from this bit is 0.
14:12
Max Read Request Size — RO. Hardwired to 0 enabling 128B maximum read request
size.
11
No Snoop Enable (NSNPEN) — R/W.
0 = The Intel
®
High Definition Audio controller will not set the No Snoop bit. In this
case, isochronous transfers will not use VC1 (VCi) even if it is enabled since VC1 is
never snooped. Isochronous transfers will use VC0.
1 = The Intel
®
High Definition Audio controller is permitted to set the No Snoop bit in
the Requester Attributes of a bus master transaction. In this case, VC0 or VC1 may
be used for isochronous transfers.
NOTE: This bit is not reset on D3
HOT
to D0 transition; however, it is reset by PLTRST#.
This bit is not reset by Function Level Reset.
10
Auxiliary Power Enable — RO. Hardwired to 0, indicating that Intel
®
High Definition
Audio device does not draw AUX power
9 Phantom Function Enable — RO. Hardwired to 0 disabling phantom functions.
8 Extended Tag Field Enable — RO. Hardwired to 0 enabling 5-bit tag.
7:5 Max Payload Size — RO. Hardwired to 0 indicating 128B.
4 Enable Relaxed Ordering — RO. Hardwired to 0 disabling relaxed ordering.
3 Unsupported Request Reporting Enable — R/W. Not implemented.
2 Fatal Error Reporting Enable — R/W. Not implemented.
1 Non-Fatal Error Reporting Enable — R/W. Not implemented.
0 Correctable Error Reporting Enable — R/W. Not implemented.
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